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AD9144BCPZ bảng dữ liệu(PDF) 8 Page - Analog Devices |
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8 / 126 page Data Sheet AD9144 Rev. A | Page 7 of 125 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SDO to SCLK Data Valid Window tDV 25 ns CS to SCLK Setup Time tSCS 5 ns Hold Time tHCS 2 ns 1 See Table 3 for detailed specifications for DAC update rate conditions. 2 Maximum speed for 1× interpolation is limited by the JESD interface. See Table 4 for details. 3 Maximum speed for 2× interpolation is limited by the JESD interface. See Table 4 for details. 4 See Table 4 for detailed specifications for JESD speed conditions. 5 K, F, and S are JESD204B transport layer parameters. See Table 44 for the full definitions. 6 See Table 5 for detailed specifications for SYSREF to DAC clock timing conditions. MAXIMUM DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit MAXIMUM DAC UPDATE RATE DVDD12, CVDD12 = 1.2 V ± 5% 2.23 GSPS DVDD12, CVDD12 = 1.2 V ± 2% 2.41 GSPS DVDD12, CVDD12 = 1.3 V ± 2% 2.80 GSPS JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 4. Parameter Test Conditions/Comments Min Typ Max Unit HALF RATE SVDD12 = 1.2 V ± 5% 5.75 8.92 Gbps SVDD12 = 1.2 V ±2% 5.75 9.42 Gbps SVDD12 = 1.3 V ± 2% 5.75 10.64 Gbps FULL RATE SVDD12 = 1.2 V ± 5% 2.88 4.63 Gbps SVDD12 = 1.2 V ± 2% 2.88 4.93 Gbps SVDD12 = 1.3 V ± 2% 2.88 5.52 Gbps OVERSAMPLING SVDD12 = 1.2 V ± 5% 1.44 2.31 Gbps SVDD12 = 1.2 V ± 2% 1.44 2.46 Gbps SVDD12 = 1.3 V ± 2% 1.44 2.76 Gbps |
Số phần tương tự - AD9144BCPZ |
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Mô tả tương tự - AD9144BCPZ |
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