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ADE9078 bảng dữ liệu(PDF) 8 Page - Analog Devices |
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ADE9078 bảng dữ liệu(HTML) 8 Page - Analog Devices |
8 / 108 page Data Sheet ADE9078 Rev. 0 | Page 7 of 107 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS MISO, IRQ0, and IRQ1 VDD = 2.7 V Output Voltage High, VOH 2.4 V ISOURCE = 1 mA Low, VOL 0.8 V ISINK = 4 mA CF1, CF2, CF3, and CF4 VDD = 2.7 V Output Voltage High, VOH 2.4 V ISOURCE = 3 mA Low, VOL 0.8 V ISINK = 8 mA LOW DROPOUT REGULATORS (LDOs) AVDD 1.9 V See the Power-On Sequence section DVDD 1.7 V POWER SUPPLY For specified performance VDD 2.7 3.3 3.63 V Supply Current (VDD) VDD = 3.63 V Power Save Mode 0 (PSM0) 10 12 mA Normal mode, seven ADCs enabled 9.5 11 mA Normal mode, seven ADCs enabled, total reactive power computation disabled 10.5 12 mA Normal mode, seven ADCs enabled, waveform buffer enabled 10 11.6 mA Normal mode, six ADCs enabled Power Save Mode 1 (PSM1) 9 10.6 mA Fast rms, active power, and total reactive power measurement within 30 ms for tamper detection Power Save Mode 2 (PSM2) 115 200 μA Compares current to threshold, AVDD = 0 V, DVDD = 0 V Power Save Mode 3 (PSM3) 50 200 nA Idle, AVDD = 0 V, DVDD = 0 V 1 Throughout this data sheet, multifunction pins, such as CF3/ZX, are referred to either by the entire pin name or by a single function of the pin, for example, CF3, when only that function is relevant. 2 Tested during device characterization. TIMING CHARACTERISTICS Table 2. Parameter Symbol Min Typ Max Unit SS to SCLK Edge tSS 10 ns SCLK Frequency 10 MHz SCLK Low Pulse Width tSL 40 ns SCLK High Pulse Width tSH 40 ns Data Output Valid After SCLK Edge tDAV 40 ns Data Input Setup Time Before SCLK Edge tDSU 10 ns Data Input Hold Time After SCLK Edge tDHD 10 ns Data Output Fall Time tDF 10 ns Data Output Rise Time tDR 10 ns SCLK Fall Time tSF 10 ns SCLK Rise Time tSR 10 ns MISO Disable After SS Rising Edge tDIS 100 ns SS High After SCLK Edge tSFS 0 ns |
Số phần tương tự - ADE9078 |
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Mô tả tương tự - ADE9078 |
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