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ADRF5040BCPZ bảng dữ liệu(PDF) 6 Page - Analog Devices

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ADRF5040
Data Sheet
Rev. A | Page 6 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PACKAGE
BASE
GND
2
1
3
4
5
6
18
17
16
15
14
13
GND
GND
GND
RFC
GND
GND
GND
VSS
V2
V1
VDD
GND
ADRF5040
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF/DC GROUND OF THE
PRINTED CIRCUIT BOARD (PCB).
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 4 to 7, 9, 10, 12, 13,
18, 19, 21, 22, 24
GND
Ground. The package bottom has an exposed metal pad that must connect to the printed circuit
board (PCB) RF/dc ground. See Figure 6 for the GND interface schematic.
3
RFC
RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required
if the RF line potential is not equal to 0 V dc.
8
RF4
RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
11
RF3
RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
14
VSS
Negative Supply Voltage Pin.
15
V2
Control Input Pin 2. See Table 2 and Table 6.
16
V1
Control Input Pin 1. See Table 2 and Table 6.
17
VDD
Positive Supply Voltage.
20
RF2
RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
23
RF1
RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
EPAD
Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
Table 6. Truth Table
Digital Control Inputs
Signal Path State
V1
V2
Low
Low
RFC to RF1
High
Low
RFC to RF2
Low
High
RFC to RF3
High
High
RFC to RF4


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