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MC143421FU bảng dữ liệu(PDF) 8 Page - Motorola, Inc |
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MC143421FU bảng dữ liệu(HTML) 8 Page - Motorola, Inc |
8 / 11 page MC143421 MOTOROLA 8 PERIPHERAL INTERFACE BUS Pin Description Pin Signal Type Description RESET Output Reset Signal, Active Low READ Output Read Command Pulse Signal, Active Low WRITE Output Write Command Pulse Signal, Active Low ha[3:0] Output 4–Bit Address Bus hd[7:0] In/Out 8–Bit Data Bus Address Mapping A31:A8 A7 A6 A5 A4 A3 A2 A1 A0 PCI A31 to A8 equal to config register 10h 1 1 ha [3] ha [2] ha [1] ha [0] X X A31 to A8 from the PCI bus are compared to the value in configuration register 10h, when a match occurs and both A7 and A6 are equal to 1, the lower eight bits are mapped as fol- lows: A5 mapped to ha[3] A4 mapped to ha[2] A3 mapped to ha[1] A2 mapped to ha[0] A0 and A1 are ignored PCI Read Operation The MC143421 will translate the PCI I/O cycle to the ISA– like Peripheral Interface Bus (PIB) that connects to the pe- ripheral function. In the event of a PCI I/O read operation, and if the address is qualified for the address mapping of the PIB, the READ control signal on the PIB will be activated for at least three PCI cycles. The input data, from the eight–bit data port on the PIB, will be latched on the rising edge of the READ signal and trans- ferred to the PCI bus. The PCI address bus is driven by the MC143421 one cycle prior to the falling edge of the READ pulse and at least one cycle after the rising edge or the READ pulse. The setup and hold time for the MC143421 to successfully latch the data from the PIB is 3 ns. PCI Write Operation The write operation is complementary to the read with the same timing, the data and address information on the PIB is valid one cycle prior to the falling edge of the PIB WRITE pulse. The data will remain valid until one cycle after the ris- ing edge of the PIB WRITE pulse. The address valid time is the same as the read operation. Subsystem ID and Subvendor ID When the MC143421 is reset, the states of the hd[7:0] and ha[3:0] pins are read into the subsystem ID and subvendor ID registers. The inputs are matched to register 2Ch as shown in Table 3. Pins hd[0] and ha[0] are internally lightly pulled up, and hd[7:1] and ha[3:1] are internally lightly down. If these pins are left floating on reset, the resulting subsystem and sub- vendor IDs will be 1. External pullups and pulldowns are re- quired for unique subvendor and subsystem IDs. Device Class The MC143421 is classified as a PCI Multimedia Device. Pins 77 and 78 are internally lightly pulled down, and can be left as no connects, or externally pulled down. If either of these pins are pulled up, it will result in an invalid vendor and device ID. Table 3. Register 2Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 ha3 ha2 ha1 ha0 Subsystem ID 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 hd7 hd6 hd5 hd4 hd3 hd2 hd1 hd0 Subvendor ID |
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