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MC141543P bảng dữ liệu(PDF) 6 Page - Motorola, Inc |
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MC141543P bảng dữ liệu(HTML) 6 Page - Motorola, Inc |
6 / 14 page MC141543 MOTOROLA 6 ADDRESS ROW COLUMN COLUMN X: don’t care D: valid data FORMAT BIT 0 1 2 3 4 5 6 7 D D D D X X X 1 D D D D D X 0 0 D D D D D X 1 0 a, b a, b, c c Figure 4. Row & Column Address Bit Patterns MEMORY MANAGEMENT Internal RAM is addressed with row and column (coln) numbers in sequence. The spaces between Row 0 and Coln 0 to Row 14 and Coln 29 are called display registers, and each contains a character ROM address corresponding to a display location on the monitor screen. Every data row is associated with two control registers, which are located at Coln 30 and 31 of their respective rows, to control the char- acter display format of that row. In addition, three window control registers for each of the three windows, together with three frame control registers, occupy the first 13 columns of Row 15. The user should handle the internal RAM address location with care, especially those rows with double length alphanu- meric symbols. For example, if Row n is destined to be double height on the memory map, the data displayed on screen Rows n and n+1 will be represented by the data con- tained in the memory address of Row n only. The data of the next Row n+1 on the memory map will appear on the screen as n+2 and n+3 row space, and so on. Hence, it is not neces- sary to load a row of blank data to compensate for the double row. The user should minimize excessive rows of data in memory in order to avoid overrunning the limited amount of row space on the screen. For rows with double width alphanumeric symbols, only the data contained in the even numbered columns of the memory map are shown. Odd numbered columns are treated in the same manner as double height rows. DISPLAY REGISTERS COLUMN 29 30 31 0 0 14 WINDOW 1 WINDOW 2 FRAME CRTL REG WINDOW 3 15 0 2 35 68 9 12 27 28 WINDOW AND FRAME CONTROL REGISTERS Figure 5. Memory Map |
Số phần tương tự - MC141543P |
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Mô tả tương tự - MC141543P |
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