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MC141531T bảng dữ liệu(PDF) 10 Page - Motorola, Inc |
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MC141531T bảng dữ liệu(HTML) 10 Page - Motorola, Inc |
10 / 25 page MOTOROLA 3–148 MC141531 D/C (Data / Command) This input pin tell the LCD driver the input at D0-D7 is data or com- mand. Input High for data while input Low for command. CS (CLK) (Input Clock) This pin is normal Low clock input. Data on D0-D7 are latched at the falling edge of CS. RES (Reset) An active Low pulse to this pin reset the internal status of the driver (same as power on reset). The minimum pulse width is 10 µs. D0-D7 (Data) This bi-directional bus is used for data / command transferring. R/W (Read / Write) This is an input pin. To read the display data RAM or the internal status (Busy / Idle), pull this pin High. The R/W input Low indicates a write operation to the display data RAM or to the internal setup regis- ters. OSC1 (Oscillator Input) For internal oscillator mode, this is an input for the internal low power RC oscillator circuit. In this mode, an external resistor of cer- tain value should be connected between the OSC1 and OSC2 pins for a range of internal operating frequencies (refer to Figure 1). For external oscillator mode, OSC1 should be left open. OSC2 (Oscillator Output / External Oscillator Input) For internal oscillator mode, this is an output for the internal low power RC oscillator circuit. For external oscillator mode, OSC2 will be an input pin for external clock and no external resistor is needed. VLL6 - VLL2 Group of voltage level pins for driving the LCD panel. They can either be connected to external driving circuit for external bias supply or connected internally to built-in divider circuit if internal divider is enable. For Internal DC/DC Converter enabled, a 0.1 µF capacitor to AVSS is required on each pin. C1N and C1P If Internal DC/DC Converter is enabled, a 0.1 µF capacitor is required to connect these two pins. C2N and C2P If Internal DC/DC Converter and Tripler are enabled, a 0.1 µF capacitor is required between these two pins. Otherwise, leave these pins open. C+ and C- If internal divider circuit is enabled, a 0.1 µF capacitor is required to connect between these two pins. VR and VF This is a feedback path for the gain control (external contrast con- trol) of VLL1 to VLL6. For adjusting the LCD driving voltage, it requires a feedback resistor placed between VR and VF, a gain con- trol resistor placed between VF and AVSS, a 10 µF capacitor placed between VR and AVSS. (Refer to the Application Circuit) COM0-COM16 (Row Drivers) These pins provide the row driving signal to LCD panel. Output is 0V during display off. COM16 also serves as the common driving signal in the icon mode. SEG0-SEG119 (Column Drivers) These 120 pins provide LCD column driving signal to LCD panel. They output 0V during display off. BP (Annunciator Backplane) This pin combines with Annun0-Annun2 pins to form annunciator driving part. When the annunciator circuit is enabled, it will output square wave of 30 Hz. It outputs low when oscillator is disabled. Annun0 - Annun2 (Annunciator Frontplanes) These pins are three independent annunciator driving outputs. The enabled annunciator outputs from its corresponding pin a 30Hz square wave which is 180 degrees out of phase with BP. Disabled annunciator output from its corresponding pin an square wave in- phase with BP. When all annunciators are disabled, all these pins output 0V. AVDD and AVSS AVDD is the positive supply to the LCD bias Internal DC/DC Con- verter. AVSS is ground. VCC For using the Internal DC/DC Converter, a 0.1 µF capacitor from this pin to AVSS is required. It can also be an external bias input pin if Internal DC/DC Converter is not used. Power is supplied to the LCD Driving Level Selector and HV Buffer Cell with this pin. Nor- mally, this pin is not intended to be a power supply to other compo- nent. DVDD and DVSS Power is supplied to the digital control circuit of the driver using these two pins. DVDD is power and DVSS is ground. PIN DESCRIPTIONS |
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