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MC141531 bảng dữ liệu(PDF) 11 Page - Motorola, Inc |
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MC141531 bảng dữ liệu(HTML) 11 Page - Motorola, Inc |
11 / 25 page 3–149 MC141531 MOTOROLA OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER Description of Block Diagram Module Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C pin. If D/C high, data is written to Graphic Display Data RAM (GDDRAM). D/C low indicates that the input at D0-D7 is interpreted as a Command. Reset is of same function as Power ON Reset (POR). Once RES received the reset pulse, all internal circuitry will back to its initial sta- tus. Refer to Command Description section for more information. MPU Parallel Interface The parallel interface consists of 8 bi-directional data lines (D0- D7), R/W, and the CS. The R/W input High indicates a read opera- tion from the Graphic Display Data RAM (GDDRAM). R/W input Low indicates a write operation to Display Data RAM or Internal Com- mand Registers depending on the status of D/C input. The CS input serves as data latch signal (clock). Refer to AC operation conditions and characteristics section for Parallel Interface Timing Description. Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is determined by number of row times the number of column (120x17 = 2040 bits). Figure 5 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs are provided. Column address 00H (or column address 77H) Column address 77H (or column address 00H) Page 1 Page 2 LSB MSB LSB MSB Com0 (Com15) Com15 (Com0) Row 0 Row 15 Note : The configuration in parentheses represent the remapping of Rows and Columns LSB Row 16 Page 3 Com16 Figure 5. Graphic Display Data RAM (GDDRAM) Address Map |
Số phần tương tự - MC141531 |
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Mô tả tương tự - MC141531 |
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