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MC14508BDW bảng dữ liệu(PDF) 1 Page - Motorola, Inc |
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MC14508BDW bảng dữ liệu(HTML) 1 Page - Motorola, Inc |
1 / 7 page MOTOROLA CMOS LOGIC DATA MC14508B 344 Dual 4-Bit Latch The MC14508B dual 4–bit latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The part consists of two identical, independent 4–bit latches with separate Strobe (ST) and Master Reset (MR) controls. Separate Disable inputs force the outputs to a high impedance state and allow the devices to be used in time sharing bus line applications. These complementary MOS latches find primary use in buffer storage, holding register, or general digital logic functions where low power dissipation and/or high noise immunity is desired. • 3–State Output • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable–of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/ _C From 100_C To 125_C TRUTH TABLE MR ST Disable D3 D2 D1 D0 Q3 Q2 Q1 Q0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 X X X X Latched 1 X 0 X X X X 0 0 0 0 X X 1 X X X X High Impedance X = Don’t Care CIRCUIT DIAGRAM DIS MR ST Dn (TO OTHER THREE LATCHES) VDD Qn VSS MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1995 REV 3 1/94 MC14508B L SUFFIX CERAMIC CASE 623 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBDW SOIC TA = – 55° to 125°C for all packages. P SUFFIX PLASTIC CASE 709 DW SUFFIX SOIC CASE 751E BLOCK DIAGRAM 22 20 18 16 15 14 13 10 8 6 4 3 2 1 23 21 19 17 11 9 7 5 MR ST DIS D0 D1 D2 D3 MR ST DIS D0 D1 D2 D3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 VDD = PIN 24 VSS = PIN 12 |
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