MOTOROLA CMOS LOGIC DATA

MC14000UB

2

Dual 3-Input NOR" Gate

Plus Inverter

The MC14000UB dual 3–input NOR gate plus inverter is constructed with

MOS P–channel and N–channel enhancement mode devices in a single

monolithic structure. These complementary MOS logic gates find primary

use where low power dissipation and/or high noise immunity is desired.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Swing Independent of Fanout

• Pin–for–Pin Replacement for CD4000UB

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, Vout Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

lin, lout

Input or Output Current (DC or Transient),

per Pin

± 10

mA

PD

Power Dissipation, per Package†

500

mW

Tstg

Storage Temperature

– 65 to + 150

_C

TL

Lead Temperature (8–Second Soldering)

260

_C

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

_C From 65_C To 125_C

Ceramic “L” Packages: – 12 mW/

_C From 100_C To 125_C

CIRCUIT SCHEMATIC

14 11 12 13

8

6

7

10

VSS

9

3

4

5

VDD

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

REV 3

1/94

LOGIC DIAGRAM

MC14000UB

L SUFFIX

CERAMIC

CASE 632

ORDERING INFORMATION

MC14XXXUBCP

Plastic

MC14XXXUBCL

Ceramic

MC14XXXUBD

SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 646

D SUFFIX

SOIC

CASE 751A

PIN ASSIGNMENT

11

12

13

14

8

9

10

5

4

3

2

1

7

6

OUTB

IN 1B

IN 2B

IN 3B

VDD

IN 1C

OUTC

IN 2A

IN 1A

NC

NC

VSS

OUTA

IN 3A

NC = NO CONNECTION

3

4

5

6

11

12

13

10

8

9

VDD = PIN 14

VSS = PIN 7