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MC12439 bảng dữ liệu(PDF) 2 Page - Motorola, Inc |
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MC12439 bảng dữ liệu(HTML) 2 Page - Motorola, Inc |
2 / 11 page MC12439 MOTOROLA TIMING SOLUTIONS BR1333 — Rev 6 2 1 N[1] N[0] NC XTAL_SEL M[6] M[5] M[4] XTAL1 FREF_EXT PWR_DOWN PLL–VCC S_LOAD S_DATA S_CLOCK 4 3 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 8 6 5 Figure 1. 28–Lead Pinout (Top View) P_LOAD VCC FOUT FOUT GND VCC TEST GND M[3] M[2] M[1] M[0] OE XTAL2 N[1:0] 0 0 0 1 1 0 1 1 Output Division 2 4 8 1 Input PWR_DOWN XTAL_SEL OE 0 FOUT FREF_EXT Disabled 1 FOUT/16 XTAL Enabled PIN DESCRIPTIONS Pin Name Type Function Inputs XTAL1, XTAL2 — These pins form an oscillator when connected to an external series–resonant crystal. S_LOAD Int. Pulldown This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of S_LOAD for proper operation. S_DATA Int. Pulldown This pin acts as the data input to the serial configuration shift registers. S_CLOCK Int. Pulldown This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. P_LOAD Int. Pullup This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition of P_LOAD for proper operation. M[6:0] Int. Pullup These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition of P_LOAD. M[6] is the MSB, M[0] is the LSB. N[1:0] Int. Pullup These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH transition of P_LOAD. OE Int. Pullup Active HIGH Output Enable. Outputs FOUT, FOUT — These differential positive–referenced ECL signals (PECL) are the output of the synthesizer. TEST — The function of this output is determined by the serial configuration bits T[2:0]. Power VCC — This is the positive supply for the chip, and is connected to +3.3V or 5.0V (VCC = PLL_VCC). PLL_VCC — This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This supply is connected to +3.3V or 5.0V (VCC = PLL_VCC). GND — These pins are the negative supply for the chip and are normally all connected to ground. Other PWR_DOWN Int. Pulldown LVCMOS input that forces the FOUT output to synchronously reduce its frequency by a factor of 16. FREF_EXT Int. Pulldown LVCMOS input which can be used as the PLL reference frequency. XTAL_SEL Int. Pullup LVCMOS input that selects between the XTAL and FREF_EXT PLL reference inputs. A HIGH selects the XTAL input. |
Số phần tương tự - MC12439 |
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Mô tả tương tự - MC12439 |
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