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ISL12024IRTC bảng dữ liệu(PDF) 9 Page - Intersil Corporation |
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ISL12024IRTC bảng dữ liệu(HTML) 9 Page - Intersil Corporation |
9 / 24 page 9 FN6749.1 December 15, 2011 24 Hour Time If the MIL bit of the HR register is 1, the RTC uses a 24-hour format. If the MIL bit is 0, the RTC uses a 12-hour format, and the H21 bit functions as an AM/PM indicator with a ‘1’ representing PM. The clock defaults to standard time with H21 = 0. Leap Years Leap years add the day February 29 and are defined as those years that are divisible by 4. Status Register (SR) The Status Register is located in the CCR memory map at address 003Fh. This is a volatile register only, and is used to control the WEL and RWEL write enable latches, read power status and two alarm bits. This register is separate from both the array and the Clock/Control Registers (CCR). BAT: Battery Supply - Volatile This bit set to “1” indicates that the device is operating from VBAT, not VDD. It is a read-only bit and is set/reset by hardware (ISL12024IRTCZ internally). Once the device begins operating from VDD, the device sets this bit to “0”. AL1, AL0: Alarm Bits - Volatile These bits announce if either alarm 0 or alarm 1 match the real-time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in a SR Read operation resets the flags. (Note: Only the AL bits that are set when an SR read starts will be reset). An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. RWEL: Register Write Enable Latch Volatile This bit is a volatile latch that powers up in the LOW (disabled) state. The RWEL bit must be set to “1” prior to any writes to the Clock/Control Registers. Writes to RWEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the CCR requires both the RWEL and WEL bits to be set in a specific sequence. WEL: Write Enable Latch - Volatile The WEL bit controls the access to the CCR during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR address will be ignored, although acknowledgment is still issued. The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the Status Register) or until the part powers up again. Writes to WEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. RTCF: Real-Time Clock Fail Bit - Volatile This bit is set to a ‘1’ after a total power failure. This is a read only bit that is set internally when the device powers up after having lost all power to the device. The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not result in setting the RTCF bit. The first valid write to the RTC after a complete power failure (writing one byte is sufficient) resets the RTCF bit to ‘0’. Unused Bits: Bit 3 in the SR is not used, but must be zero. The Data Byte output during a SR read will contain a zero in this bit location. TABLE 1. STATUS REGISTER (SR) ADDR 7 6 5 4 3 2 1 0 003Fh BAT AL1 AL0 0 0 RWEL WEL RTCF Default 0 0 0 0 0 0 0 1 ISL12024IRTC |
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Mô tả tương tự - ISL12024IRTC |
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