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MC145173DW bảng dữ liệu(PDF) 4 Page - Motorola, Inc

tên linh kiện MC145173DW
Giải thích chi tiết về linh kiện  Dual-Band PLL Frequency Synhesizer with ADC and Frequency Counter
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC145173DW bảng dữ liệu(HTML) 4 Page - Motorola, Inc

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MC145173
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4
DC ELECTRICAL CHARACTERISTICS (continued) (VDD = 4.5 to 5.5 V, Voltages Referenced to VSS, TA = – 40 to + 85°C)
Symbol
Parameter
Test Condition
Guaranteed
Limit
Unit
ISTBY
Maximum Standby Supply Current
Vin on Din, CLK, INPUT A, INPUT
B, INPUT C, INPUT D = VDD or
VSS; Vin on ENB = VDD; Vin on
OSCin, HF IFin, VHF IFin = VSS or
Floating (ac coupled); Vin on HFin
= VDD or VSS or Floating (ac
coupled); Vin on VHFin = Floating
(ac coupled); Dout tied to VDD or
VSS through 100 kΩ resistor; Oth-
er Outputs Open
30
µA
Idd
Maximum Operating Supply Current
Vin on Din, CLK, INPUT A, INPUT
B, INPUT C, INPUT D = VDD or
VSS; Dout tied to VDD or VSS
through 100 k
Ω resistor; Vin on
ENB = VDD; OSCin = 10.35 MHz
@ 1 V p–p; VHFin = 120 MHz @
210 mV p–p; VHF IFin = 10.7 MHz
@ 210 mV p–p
12
mA
ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — VHF PDout
(Iout ≤ 2.5 mA, VDD = 4.5 to 5.5 V, Voltages Referenced to VSS)
Parameter
Test Condition
Guaranteed
Limit
Unit
Maximum Source Current Variation (Part–to–Part)
Vout = 0.5 x VDD
± 20
%
Maximum Sink–vs–Source Mismatch (Note 3)
Vout = 0.5 x VDD
12
%
Output Voltage Range (Note 3)
Iout variation ≤ 20%
1.25 to VDD – 1.25 V
V
NOTES:
1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor value.
3. This parameter is guaranteed for any specific temperature within – 40 to + 85
°C.
ADC CHARACTERISTICS (TA = – 40 to 85°C, VDD = 4.5 to 5.5 V, fOSC = 9.5 to 10.4 MHz)
Parameter
Test Condition
Guaranteed
Limit
Unit
Resolution
6
Bits
Conversion Time
Per Figure 1
3584
OSCin
Cycles
Maximum Nonlinearity
Vin = VSS + (0.1 x VDD) to
VDD – (0.09 x VDD)
± 1.5
LSBs
EOC FLIP–FLOP OUTPUT
(INTERNAL)
ENB
Din
CONVERSION TIME
SET BIT C7 HIGH
IN C REGISTER
ADC READY TO BE
READ VIA SERIAL PORT
Figure 1.


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