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MC145173 bảng dữ liệu(PDF) 10 Page - Motorola, Inc |
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MC145173 bảng dữ liệu(HTML) 10 Page - Motorola, Inc |
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10 / 33 page  MC145173 MOTOROLA 10 A P–channel MOSFET tied to VDD is used to drive this open– drain output. Thus, an external pull–down device is required at this pin. This output is disabled and assumes the high–im- pedance state in the VHF mode per bit HF/VHF in the R reg- ister. (See Figure 18.) REFout is capable of operation to 10.4 MHz; see the AC Electrical Characteristics table. If unused, the pin may be floated or tied to VDD. FREQUENCY COUNTER INPUT PINS HF IFin HF Intermediate–Frequency Input (Pin 10) This pin feeds an on–chip amplifier. The amp drives the F counter when the HF/VHF bit in the R register is low. (See Figure 18.) The signal driving this pin is normally sourced from the IF (intermediate frequency) circuit in the radio and is ac coupled. The input capaci- tance is approximately 6 pF. This input is optimized for use with frequencies around 450 kHz. An on–chip low–pass filter is employed to roll off re- sponse above 1 MHz. In addition, for further suppression of high– frequency signals, the Kuligowski Acceptor Circuit may be engaged via the K bit in the R register. This is a digital integrator which allows acceptance of frequencies only below the frequency at the OSCin pin divided by 8. In the standby mode, HF IFin is pulled low by an on–chip FET. If not used, this pin should be tied to VSS. VHF IFin VHF Intermediate–Frequency Input (Pin 11) This pin feeds an on–chip amplifier. The amp drives the F counter when the HF/VHF bit in the R register is high. (See Figure 18.) The signal driving this pin is normally sourced from the IF circuit in the radio and is ac coupled. The input capacitance is approximately 6 pF. Usually, the frequency of the signal driving this pin is about 10.7 MHz. For signals which swing from at least the VIL to VIH levels listed in the DC Electrical Characteristics table, dc cou- pling may be used. Also, for signals less than the minimum frequencies in the AC Electrical Characteristics table, dc coupling with at least VIL and VIH levels is a requirement. The F counter is a static counter and may be operated down to dc. However, wave shaping by a CMOS buffer may be re- quired to ensure fast rise and fall times into the VHF IFin pin. In the standby mode, VHF IFin is forced to a high–imped- ence state. If not used, this pin should be tied to VSS. LOOP PINS HFin, VHFin High Frequency Input, Very High Frequency Input (Pins 16, 15) These pins feed on–chip amplifiers which drive the N counter; the HF/VHF bit in the R register determines which input is selected. (See Figure 18.) These signals are normal- ly sourced from external voltage–controlled oscillators (VCOs), and are ac–coupled. (See Figures 10 and 11.) The input capacitance is approximately 6 pF. For small divide ra- tios, the maximum frequency is limited to the divide ratio times 1 MHz. (Reason: the phase/frequency detectors are limited to a maximum frequency of 1 MHz.) For signals which swing from at least the VIL to VIH levels listed in the DC Electrical Characteristics table, dc cou- pling may be used. Also, for signals less than the minimum frequencies in the AC Electrical Characteristics table, dc coupling with at least VIL and VIH levels is a requirement. The N counter is a static counter and may be operated down to dc. However, wave shaping by a CMOS buffer may be re- quired to ensure fast rise and fall times into the HFin and VHFin pins. Each rising edge on these pins cause the N counter to decrement by one. In the standby mode, HFin is forced to a high–impedence state, and VHFin is pulled low by an on–chip FET. If not used, these pins should be tied to VSS. HF PDout Single–Ended Phase/Frequency Detector Output (Pin 18) This is a three–state output for use as a loop error signal when combined with an external low–pass filter. Through use of a Motorola patented technique, the detector’s dead zone has been eliminated. Therefore, the phase/frequency detec- tor is characterized by a linear transfer function. The opera- tion of the phase/frequency detector is described below and is shown in Figure 16. POL bit (R23) in the R register = low (see Figure 18) Frequency of fV > fR or Phase of fV Leading fR: negative pulses from high impedance Frequency of fV < fR or Phase of fV Lagging fR: positive pulses from high impedance Frequency and Phase of fV = fR: essentially high–imped- ance state; voltage at pin determined by loop filter POL bit (R23) = high Frequency of fV > fR or Phase of fV Leading fR: positive pulses from high impedance Frequency of fV < fR or Phase of fV Lagging fR: negative pulses from high impedance Frequency and Phase of fV = fR: essentially high–imped- ance state; voltage at pin determined by loop filter This output is enabled and disabled via the HF/VHF bit in the R register. HF PDout is forced to the high–impedance state when disabled. This pin should be floated when it is not used. VHF PDout Single–Ended Phase/Frequency Detector Output (Pin 21) This is a three–state current–source/sink output for use as a loop error signal when combined with an external low–pass filter. The phase/frequency detector is characterized by a lin- ear transfer function. The operation of the phase/frequency detector is described below and is shown in Figure 16. POL bit (R23) in the R register = low (see Figure 18) Frequency of fV > fR or Phase of fV Leading fR: current– sinking pulses from a floating state Frequency of fV < fR or Phase of fV Lagging fR: current– sourcing pulses from a floating state Frequency and Phase of fV = fR: essentially a floating state; voltage at pin determined by loop filter POL bit (R23) = high Frequency of fV > fR or Phase of fV Leading fR: current– sourcing pulses from a floating state Frequency of fV < fR or Phase of fV Lagging fR: current– sinking pulses from a floating state |
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