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MC145074 bảng dữ liệu(PDF) 7 Page - Motorola, Inc |
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MC145074 bảng dữ liệu(HTML) 7 Page - Motorola, Inc |
7 / 14 page MC145074 7 MOTOROLA $80000 $7FFFF 1 20–BIT DIGITAL INPUT SCALER OUTPUT SCALER TRANSFER FUNCTION 3/4 SCALE = – 2.5 dB 1 – IDEAL 2 – ACTUAL 3 – COMPENSATED 3 2 Figure 10. Offset Scaler Operation SERIAL INTERFACE AND CONTROL LOGIC The serial interface and control logic of the MC145074 may be configured to accept 16, 18, or 20–bit data words by applying the appropriate logic levels to the RES1 and RES0 pins. The DMODE input pin configures the serial interface to accept 2’s complement data (MSB first) in a dual data pin or single pin, multiplexed input format. It should be noted that in some cases when using the single data pin input mode and a large OSR, the BCLK rate may be too high for some DSPs, unless an interface circuit is added. Figure 9 shows the avail- able serial interface formats of the MC145074. When operating in a dual data pin mode, 2’s complement data words are serially input from the DIR and DIL pins as shown in Figure 12. A rising edge on BCLK serially shifts in the data present on the DIR and DIL inputs. After all data bits of an input word are shifted in, a falling edge on WCLK latches the data word into the MC145074. The BCLK can be a continuous clock as long as the serial input data word is right justified in the word time, or as long as there exists one and only one BCLK cycle for every data bit input to the device. When operating in a single pin multiplexed mode, the DIR input pin is reconfigured as the DILR pin. Left and right chan- nel serial input data is multiplexed into the MC145074 on the DILR pin, and is serially shifted into the part using BCLK as shown in Figure 13. When WDLY is low, left channel data is latched into the part on the rising edge of WCLK, and right channel data is latched on the falling edge of WCLK. As in the dual data pin mode, the BCLK can be either an asynchro- nous or continuous clock as long as the serial input data word is right justified in the word time. Forcing WDLY high al- lows the WCLK cycle to appear one clock cycle early as shown in Figure 14. |
Số phần tương tự - MC145074 |
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Mô tả tương tự - MC145074 |
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