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MC145074 bảng dữ liệu(PDF) 5 Page - Motorola, Inc |
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MC145074 bảng dữ liệu(HTML) 5 Page - Motorola, Inc |
5 / 14 page MC145074 5 MOTOROLA PIN DESCRIPTIONS VDD Positive Device Supply (Pin 1) VDD is the positive supply, nominally + 5 volts. STBY Active–Low Standby Input (Pin 2) A low level on the STBY pin will force the device into a standby state. If the device is being operated in the master mode (MSTR = 1), the WCLK internal divider can be programmed using the DIR/DILR, and BCLK pins while the STBY pin is active. When the device is in standby, the DOL and DOR pins will output a 50% duty cycle data stream that will generate a 1/2 scale analog output, when averaged through the output filter. DIL/WDLY Left Channel Data/Word Clock Delay Input (Pin 3) When the DMODE pin is low, this pin is the left channel (MSB first) 2’s complement serial data input. When the DMODE pin is high, this pin controls the WCLK delay. A high level on this pin will delay the WCLK an additional clock cycle internal to the device. DIR/DILR Right Channel Data/Multiplexed Left – Right Data Input (Pin 4) When the DMODE pin is low, this pin is the right channel (MSB first) 2’s complement serial data input. When the DMODE pin is high, this pin is the multiplexed left then right channel data input. If the part is being operated in the master mode (MSTR = 1), the WCLK internal divider can be pro- grammed by clocking control word data onto this pin with the BCLK pin while the device is in the standby mode (STBY = 0). BCLK Bit Clock Input (Pin 5) The BCLK pin provides the serial bit shift clock for the left and right channel data in all modes of operation. A rising edge on the BCLK pin shifts serial data into the device. WCLK Word Clock Output/Input (Pin 6) The WCLK pin is used to latch the shifted serial data word into the device. The MC145074 can accept an external word clock when in the slave mode, or can use an internally generated word clock when operating in the master mode. When DMODE is low, left and right channel data is latched into the device on the falling edge of WCLK. When DMODE is high, left channel data is latched on the rising edge of WCLK and right channel data is latched on the falling edge of WCLK with both channel inputs being input to the modulator on the next rising edge of WCLK. The internal divide ratio used to generate WCLK, as well as the rising or falling edge latching of the input data can be programmed using the DIR/ DILR and BCLK pins while the device is in the standby mode. MSTR Active–High Master Mode Select Input (Pin 7) A high level on the MSTR pin will select the master mode of operation. In the master mode, the MC145074 will generate and output a word clock signal on the WCLK pin. A low level on the MSTR pin will place the MC145074 in the slave mode, and the WCLK signal must be provided by an external source. The default master mode divide rate is MODCLK/64. VSS Device Ground (Pin 8) VSS is normally connected to ground. DOR Right Channel Data Output (Pin 9) DOR is the right channel modulator data output. DIV2 Master Clock Divide Control Input (Pin 10) DIV2 is the Xin divide by two control pin. When cleared, the Xin pin directly provides the modulator clock (MODCLK), and the data output bit streams are not chopped. When this pin is set, the Xin clock is divided by two to provide the modulator clock and the output data bit stream is chopped at the Xin fre- quency using an alternating 1,0 chop. The chop is used to reduce even order distortion for a stand–alone application without the MC145076. The reconstructed output signal will drop 6dB due to the chopping. Xout Master Clock Output (Pin 11) Xout is the inverted output signal of Xin and may be used for a buffered clock output or for a crystal oscillator. Xin Master Clock Input (Pin 12) Xin is the input clock pin for the MC145074, and may be used with Xout as the inverter for a crystal oscillator. DMODE Data Mode Input (Pin 13) A low level on the DMODE pin will select the dual data pin mode of operation. In this mode, the serial input data is entered on the DIR and DIL pins. A high level on the DMODE pin selects the multiplexed mode of operation. In this mode, the left and right channel serial input data must be multi- plexed on the DIR/DILR pin. RES0 and RES1 Input Data Resolution Pins (Pins 14, 15) The RES0 and RES1 pins select the length of the serial data word input to the MC145074. The serial input data can be 16, 18, or 20–bits in length with the most significant bits clocked in first. Figure 9 lists the serial interface formats. DOL Left Channel Data Output (Pin 16) DOL is the left channel modulator data output. |
Số phần tương tự - MC145074 |
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Mô tả tương tự - MC145074 |
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