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MC145073DW bảng dữ liệu(PDF) 7 Page - Motorola, Inc

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Giải thích chi tiết về linh kiện  Dual 16-Bit Stereo Audio Sigma-Delta ADC
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MC145073DW bảng dữ liệu(HTML) 7 Page - Motorola, Inc

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MOTOROLA
MC145073
7
AC ELECTRICAL SPECIFICATIONS
(Full temperature and voltage ranges per Operation Ranges table. All timing parameters measured with respect to 30% and 70% of VDD(D)
unless otherwise noted.)
Figure
Symbol
Parameter
Divide
Ratio
Min
Max
Unit
6
1/tclk
Master Clock (CLK) Frequency (Note 1)
3.072
18.432
MHz
6
1/tclki
Internal Clock Frequency, CLKI (Note 1)
tclki = 1/(fclk/Divide Ratio)
3.072
6.144
MHz
6
twch
Master Clock High, CLK
1
2, 3
38
20
ns
6
twcl
Master Clock Low, CLK
1
2, 3
38
20
ns
7
tsync
Sync Period (Master and Slave Modes)
128 * tclki
128 * tclki
ns
7
twsh
Sync High (Slave Mode)
20
126 * tclki
ns
Cin
Input Capacitance
(Except for Left/Right Channel Inputs)
20
pF
Master Mode: ISLAV = 0
8
tsclk
SCLK Period
2 * tclki
2 * tclki
ns
8
twl/twh
SCLK Duty Cycle
0.667
1.50
8
tCSY
Propagation Delay (Note 2)
CLK Falling Edge to SYNC
CLK Rising Edge to SYNC
CLK Falling Edge to SYNC
1
2
3
40
tclk + 40
2 * tclk + 40
ns
ns
ns
8
tCSC
Propagation Delay (Note 2)
CLK Falling Edge to SCLK
CLK Rising Edge to SCLK
CLK Falling Edge to SCLK
1
2
3
40
tclk + 40
2 * tclk + 40
ns
ns
ns
8
tCDV
Propagation Delay (Note 2)
CLK Falling Edge to Serial Data Valid, SDO
CLK Rising Edge to Serial Data Valid, SDO
CLK Falling Edge to Serial Data Valid, SDO
1
2
3
40
tclk + 40
2 * tclk + 40
ns
ns
ns
Slave Mode: ISLAV = 1
9
tsu
Setup Time (Note 3)
SCLK to Rising Edge of CLK
15
ns
9
th
Hold Time (Note 3)
SCLK to Rising Edge of CLK
0
ns
9
tsclkh
SCLK High
20
ns
9
tsclkl
SCLK Low
20
ns
9
tsu
Setup Time (Note 3)
SYNC to Rising Edge of CLK
15
ns
9
th
Hold Time (Note 3)
SYNC to Rising Edge of CLK
0
ns
tCDV
Propagation Delay
Clk Rising Edge to Serial Data Valid, SDO
1
2
3
twch
tclk
tclk + twch
twch + 40
2 * tclk + 40
3 * tclk + twch + 40
NOTES:
1. The internal clock frequency, or input sampling frequency (CLKI) is governed by the divide mode and output data rate.
The divide mode can be either 1, 2, or 3. The output data rate ranges from 24 kHz to 48 kHz.
The minimum clock frequency of 3.072 MHz corresponds to an output data rate of 24 kHz with the device in the clock divide by one mode.
The maximum clock frequency of 18.432 MHz corresponds to an output data rate of 48 kHz with the device in the clock divide by three mode.
2. Propagation delay is measured with a capacitive load of 50 pF.
3. In the slave mode, SYNC or SCLK transitions can occur anywhere except 0 to – 5 ns relative to the CLK rising edge.


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