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MC145073 bảng dữ liệu(PDF) 9 Page - Motorola, Inc |
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MC145073 bảng dữ liệu(HTML) 9 Page - Motorola, Inc |
9 / 16 page MOTOROLA MC145073 9 PIN DESCRIPTIONS ANALOG PINS AIN(+L), AIN(–L) Left Channel Analog Inputs (Pins 1, 2) These two pins comprise the left channel analog differ- ential inputs. The voltage range of signals applied to these pins is from VSS(A) to VDD(A). A positive full–scale input to the A/D is defined as a difference of 3.8 V p–p between AIN(+L) and AIN(–L). AIN(+R), AIN(–R) Right Channel Analog Inputs (Pins 24, 23) These two pins comprise the right channel analog differ- ential inputs. The voltage range of signals applied to these pins is from VSS(A) to VDD(A). A positive full–scale input to the A/D is defined as a difference of 3.8 V p–p between AIN(+R) and AIN(–R). REF Output of the Internal Voltage Reference (Pin 3) The nominal value of this internal voltage reference is 2 V. The output of the reference is brought out to this pin to facili- tate filtering. For proper device operation, this pin should be decoupled to V SS(A) with a 1.0 µF electrolytic capacitor in parallel with a 0.1 µF ceramic capacitor. In order to economize on filtering capacitors, the REF pin can be connected to VAG. However, this could result in a possible degradation of performance of the device at high signal levels. VAG Output of the Internal Analog Ground Generator (Pin 22) Analog ground is used to bias the internal analog circuits and is nominally 2 V. VAG is brought out to this pin to facilitate filtering. This pin should be decoupled to VSS(A) with a 1.0 µF electrolytic capacitor in parallel with a 0.1 µF ceramic capaci- tor for normal device operation. DIGITAL PINS CLK Master Clock Input (Pin14) This pin is the master clock input for the device. Analog input signals to the MC145073 are sampled at a rate equal to this clock frequency divided by 1, 2, or 3, depending on the state of clock mode pins CSEL1,0. The serial data output rate is equal to the input sample rate divided by 128. For example, if CLK is running at a 12.288 MHz rate, and divide by 2 is selected, then the output data rate is (12.288 MHz/2)/128 = 48 kHz. For more detail, see the Sum- mary of Operating Modes section. SYNC Serial Interface Frame Sync Input/Output (Pin 11) The SYNC pin is an input or output depending on the state of the ISLAV pin. The SYNC signal resets and synchronizes the serial interface transmitter and receivers, as well as most internal clocks. Left channel serial output data is transmitted when the SYNC signal is active high, and right channel data is transmitted when the SYNC signal is low. See the Serial Interface Description section for more information. SCLK Serial Interface Clock Input/Output (Pin 12) The SCLK pin is an input or output depending on the state of the ISLAV pin. Serial output data is clocked out of the MC145073 on the rising edge of SCLK. When SCLK is an input, it is reclocked by the internal sample rate clock, CLKI, before being used by the MC145073 to clock out the serial data. This reclocking ensures that rapid current changes through the SDO pin do not affect the analog performance of the device. See the Serial Interface Description section for more information. SDO Serial Interface Data Output (Pin 13) The A/D conversion results for the left and right channels are output on this pin. Data is shifted out of the MC145073 MSB first, with the left channel data preceding the right chan- nel data. The serial output data is clocked out on the rising edge of SCLK. See the Serial Interface Description section for more information. FTP Factory Test Mode Inputs (Pins 9, 10) These pins should be connected to VSS(A) for normal device operation. CSEL0, CSEL1 Clock Divide Mode Select Inputs (Pins 21, 20) The device master clock input is divided by 1, 2, or 3, or the device is placed in a power–down mode depending on the state of these pins. See the Summary of Operating Modes section for more information. FSEL FIR Filter Response Select Input (Pin 19) A low level on the FSEL input selects a FIR filter transition band from 20 to 25.8 kHz at the 48 kHz output data rate. A high level on the FSEL pin selects a filter transition band from 20 to 24 kHz at the 44.1 kHz output data rate. See the Sum- mary of Operating Modes section for more information. ISYNC Serial Interface Sync Format Select Input (Pin 18) A low level input on the ISYNC pin selects a SYNC rising edge one SCLK cycle before the initiation of a serial data transfer. A high level on the ISYNC pin will select a SYNC rising edge that is coincident with the initiation of a serial data transfer. See the Summary of Operating Modes and the Serial Interface Description sections for more information. ISLAV Serial Interface Slave Mode Select Input (Pin 17) This pin controls the direction of the serial interface SYNC and SCLK signals. A low level on the ISLAV pin will configure the SYNC and SCLK pins as outputs, while a high level on the ISLAV pin will configure the SYNC and SCLK pins as in- puts. See the Summary of Operating Modes and the Serial Interface Description sections for more information. |
Số phần tương tự - MC145073 |
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Mô tả tương tự - MC145073 |
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