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MC144112 bảng dữ liệu(PDF) 2 Page - Motorola, Inc

tên linh kiện MC144112
Giải thích chi tiết về linh kiện  Quad Six-Bit Digital-to-Analog Converter
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC144112 bảng dữ liệu(HTML) 2 Page - Motorola, Inc

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MC144112
MOTOROLA
2
MAXIMUM RATINGS* (Voltages referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage
VDD
– 0.5 to + 5.5
V
Input Voltage, All Inputs
Vin
– 0.5 to VDD + 0.5
V
DC Input Current, per Pin
I
± 10
mA
Power Dissipation (Per Output)
TA = 70°C
TA = 85°C
POH
50
20
mW
Power Dissipation (Per Package)
TA = 70°C
TA = 85°C
PD
150
50
mW
Storage Temperature Range
Tstg
– 65 to + 150
°C
* Maximum Ratings are those values beyond which damage to the device may occur.
ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS, VDD = 2.7 to 5.5 V, TA = – 40 to 85°C unless otherwise indicated)
Symbol
Parameter
Test Conditions
VDD
Min
Max
Unit
VIH
High–Level Input Voltage (Din, ENB, CLK)
2.7
4.5
5.5
2.03
3.15
3.85
V
VIL
Low–Level Input Voltage (Din, ENB, CLK)
2.7
4.5
5.5
0.67
1.35
1.65
V
IOH
High–Level Output Current (Dout)
Vout = VDD – 0.5 V
2.7
4.5
0.3
1.1
mA
IOL
Low–Level Output Current (Dout)
Vout = 0.5 V
2.7
4.5
1.0
1.8
mA
ISS
Quiescent Supply Current (per Package)
Iout = 0 µA, All DAC Outputs = Zero
2.7
4.5
5.5
1.25
2.10
2.50
mA
Iout = 0 µA, All DAC Outputs = Full Scale
5.5
30
µA
Iin
Input Leakage Current (Din, ENB, CLK)
Vin = VDD or 0 V
5.5
1
µA
Vnonl
Integral Nonlinearity (Rn Out)
See Figure 1
– 1 1/4
1/4
LSB
Vstep
Differential Nonlinearity (Rn Out)
See Figure 2
3/4
3/4
LSB
Voffset
Offset from VSS
Din = $00, See Figure 1
1/4
1 3/4
LSB
SWITCHING CHARACTERISTICS
(VDD = 2.7 to 5.5 V, Voltages referenced to VSS, TA = – 40 to 85°C, CL = 50 pF, Input tr = tf = 20 ns unless otherwise indicated)
Symbol
Parameter
Min
Max
Unit
twH
Positive Pulse Width, CLK (Figures 3 and 4)
166
ns
twL
Negative Pulse Width, CLK (Figures 3 and 4)
166
ns
tsu
Setup Time, ENB to CLK (Figures 3 and 4)
135
ns
tsu
Setup Time, Din to CLK (Figures 3 and 4)
55
ns
th
Hold Time, CLK to ENB (Figures 3 and 4)
135
ns
th
Hold Time, CLK to Din (Figures 3 and 4)
55
ns
tr, tf
Input Rise and Fall Times, CLK
100
µs
Cin
Input Capacitance
10
pF
fclk
Serial Data Clock Frequency (Refer to twH and twL Above) (Figures 3 and 4)
dc
3
MHz
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields; however, it is ad-
vised that precautions be taken to avoid
application of voltage higher than maximum
rated voltages to this high–impedance circuit.
For proper operation it is recommended that
Vin and Vout be constrained to the range VSS ≤
(Vin or Vout) ≤VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD).


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