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MC141511A bảng dữ liệu(PDF) 7 Page - Motorola, Inc |
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MC141511A bảng dữ liệu(HTML) 7 Page - Motorola, Inc |
7 / 17 page 3–25 MC141511A MOTOROLA VDD AND VSS The main dc power is supplied to the part by these two connec- tions. VDD is the most-positive supply level for logic circuitry and VSS is ground. VLCD This supply connection provides the voltage level for the segment drivers and is connected to the Vout connection of the MC68HC05L10 MCU. VSEGL, VSEGH These inputs are connected to V2 and V3 of an external voltage divider. See Figure 4. D0 - D7 These connections form an eight bit wide bidirectional data bus which are connected to D0 through D7 of the MC68HC05L10. A0 - A9 These inputs form a ten-bit wide address bus for addressing the display RAM and are connected to A0 through A9 of the MC68HC05L10. BPSYNC This input is a periodic active-low signal from the MC68HC05L10 for timing synchronization. BPSYNC is connected to FRM of MC68HC05L10. See Figure 5. BPCLK This input may be run as high as 4.096 kHz (50% duty cycle). It provides the required frame frequency for the segment driver. It is con- nected to BPCLK of the MC68HC05L10. Thus, the frequency is usually 2.048 kHz. See Figure 5. PHI2 This input is a bus clock input that is used for data bus timing syn- chronization. It is connected to P02 of MC68HC05L10. SEG0 - SEG127 These 128 output lines provide the frontplane drive signals to the LCD panel. These outputs are forced to a low level while display is turned off. Any unused segment outputs should be left open. CE This is an active low chip enable input and is connected to either CS1, CS2, CS3 or CS4 of the MC68HC05L10. LRS The left-right selection input defines the direction of the segment driver display. See Figure 8. 0 or Low = SEG 0 - 127 1 or High = SEG 127 - 0 MS This input selects how display RAM is addressed. Either a 1:32 or 1:41 multiplex ratio is possible. 0 or Low = 1:32 multiplex addressing 1 or High = 1:41 multiplex addressing R/W This input indicates which direction the data is to be passed over the data bus. When R/W is low, the LCD driver reads data from the data bus (D0-D7). When R/W is high, the LCD driver writes data to the data bus (D0-D7). This input is connected to R/W of MC68HC05L10. TEST Allowing this connection to float or connecting it to VSS (GND) places the part in the normal mode of operation. This input has an on- chip pulldown resistance of approximately 1M. PIN DESCRIPTIONS Figure 4. External Voltage Divider V3 V2 |
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Mô tả tương tự - MC141511A |
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