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MC14510B bảng dữ liệu(PDF) 1 Page - Motorola, Inc |
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MC14510B bảng dữ liệu(HTML) 1 Page - Motorola, Inc |
1 / 10 page MOTOROLA CMOS LOGIC DATA 351 MC14510B BCD Up/Down Counter The MC14510B synchronous up/down BCD counter is constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. The counter consists of type D flip–flop stages with a gating structure to provide type T flip–flop capability. This counter can be preset by applying the desired value in BCD to the Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE) high. The direction of counting is controlled by applying a high (for up counting) or a low (for down counting) to the UP/DOWN input. The state of the counter changes on the positive transition of the clock input. Cascading can be accomplished by connecting the Carry Out to the Carry In of the next stage while clocking each counter in parallel. The outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the Reset (R) pin. This CMOS counter finds primary use in up/down and difference counting. Other applications include: (1) Frequency synthesizer applications where low power dissipation and/or high noise immunity is desired, (2) Analog–to– digital and digital–to–analog conversions, and (3) Magnitude and sign generation. • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Internally Synchronous for High Speed • Logic Edge–Clocked Design — Count Occurs on Positive Going Edge of Clock • Asynchronous Preset Enable Operation • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range. MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/ _C From 100_C To 125_C TRUTH TABLE Carry In Up/Down Preset Enable Reset Clock Action 1 X 0 0 X No Count 0 1 0 0 Count Up 0 0 0 0 Count Down X X 1 0 X Preset X X X 1 X Reset X = Don’t Care NOTE: When counting up, the Carry Out signal is normally high, and is low only when Q1 and Q4 are high and Carry In is low. When counting down, Carry Out is low only when Q1 through Q4 and Carry In are low. MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1995 REV 3 1/94 MC14510B L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC TA = – 55° to 125°C for all packages. P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, pre- cautions must be taken to avoid applications of any voltage higher than maximum rated volt- ages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. BLOCK DIAGRAM 1 5 9 10 15 4 12 13 3 6 11 14 2 7 PE CARRY IN R UP/DOWN CLOCK P1 P2 P3 P4 Q1 Q2 Q3 Q4 CARRY OUT VDD = PIN 16 VSS = PIN 8 |
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