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MC14489P bảng dữ liệu(PDF) 6 Page - Motorola, Inc |
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MC14489P bảng dữ liệu(HTML) 6 Page - Motorola, Inc |
6 / 20 page MC14489 MOTOROLA 6 PIN DESCRIPTIONS DIGITAL INTERFACE Data In (Pin 12) Serial Data Input. The bit stream begins with the MSB and is shifted in on the low–to–high transition of Clock. When the device is not cascaded, the bit pattern is either 1 byte (8 bits) long to change the configuration register or 3 bytes (24 bits) long to update the display register. For two chips cascaded, the pattern is either 4 or 6 bytes, respectively. The display does not change during shifting (until Enable makes a low– to–high transition) which allows slow serial data rates, if de- sired. The bit stream needs neither address nor steering bits due to the innovative BitGrabber registers. Therefore, all bits in the stream are available to be data for the two registers. Ran- dom access of either register is provided. That is, the regis- ters may be accessed in any sequence. Data is retained in the registers over a supply range of 3 to 6 V. The format is shown in Figures 7 and 8. Information on the segment de- coder is given in Table 1. Data In typically switches near 50% of VDD and has a Schmitt–triggered input buffer. These features combine to maximize noise immunity for use in harsh environments and bus applications. This input can be directly interfaced to CMOS devices with outputs guaranteed to switch near rail– to–rail. When interfacing to NMOS or TTL devices, either a level shifter (MC14504B, MC74HCT04A) or pullup resistor of 1 k Ω to 10 kΩ must be used. Parameters to be considered when sizing the resistor are the worst–case IOL of the driving device, maximum tolerable power consumption, and maxi- mum data rate. Clock (Pin 11) Serial Data Clock Input. Low–to–high transitions on Clock shift bits available at Data In, while high–to–low transitions shift bits from Data Out. The chip’s 24–1/2–stage shift regis- ter is static, allowing clock rates down to dc in a continuous or intermittent mode. The Clock input does not need to be synchronous with the on–chip clock oscillator which drives the multiplexing circuit. Eight clock cycles are required to access the configuration register, while 24 are needed for the display register when the MC14489 is not cascaded. See Figures 7 and 10. As shown in Figure 11, two devices may be cascaded. In this case, 32 clock cycles access the configuration register and 48 access the display register, as depicted in Figure 8. Cascading of 3, 4, and 5 devices is shown in Figures 12, 13, and 14, respectively. Clock typically switches near 50% of VDD and has a Schmitt–triggered input buffer. Slow Clock rise and fall times are tolerated. See the last paragraph of Data In for more in- formation. NOTE To guarantee proper operation of the power–on reset (POR) circuit, the Clock pin must NOT be floated or toggled during power–up. That is, the Clock pin must be stable until the VDD pin reaches at least 3 V. If control of the Clock pin during power–up is not practical, then the MC14489 must be reset via bit C0 in the C register. To accomplish this, C0 is re- set low, then set high. Enable (Pin 10) Active–Low Enable Input. This pin allows the MC14489 to be used on a serial bus, sharing Data In and Clock with other peripherals. When Enable is in an inactive high state, Data Out is forced to a known (low) state, shifting is inhibited, and the port is held in the initialized state. To transfer data to the device, Enable (which initially must be inactive high) is taken low, a serial transfer is made via Data In and Clock, and Enable is taken high. The low–to–high transition on Enable transfers data to either the configuration or display register, depending on the data stream length. Every rising edge on Enable initiates a blanking interval while data is loaded. Thus, continually loading the device with the same data may cause the LEDs on some banks to appear dimmer than others. NOTE Transitions on Enable must not be attempted while Clock is high. This puts the device out of synchronization with the microcontroller. Resyn- chronization occurs when Enable is high and Clock is low. This input is also Schmitt–triggered and switches near 50% of VDD, thereby minimizing the chance of loading erro- neous data in the registers. See the last paragraph of Data In for more information. Data Out (Pin 18) Serial Data Output. Data is transferred out of the shift reg- ister through Data Out on the high–to–low transition of Clock. This output is a no connect, unless used in one of the man- ners discussed below. When cascading MC14489’s, Data Out feeds Data In of the next device per Figures 11, 12, 13, and 14. Data Out could be fed back to an MCU/MPU to perform a wrap–around test of serial data. This could be part of a sys- tem check conducted at power–up to test the integrity of the system’s processor, pc board traces, solder joints, etc. The pin could be monitored at an in–line Q.A. test during board manufacturing. Finally, Data Out facilitates troubleshooting a system. DISPLAY INTERFACE Rx (Pin 8) External Current–Setting Resistor. A resistor tied between this pin and ground (VSS) determines the peak segment drive current delivered at pins a through h. Pin 8’s resistor ties into a current mirror with an approximate current gain of 10 when bit D23 = high (brighten). With D23 = low, the peak current is reduced about 50%. Values for Rx range from 700 Ω to infin- ity. When Rx = ∞ (open circuit), the display is extinguished. For proper current control, resistors having ± 1% tolerance should be used. See Figure 9. CAUTION Small Rx values may cause the chip to overheat if precautions are not observed. See Thermal Considerations. |
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Mô tả tương tự - MC14489P |
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