MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1

REV 6

10/95

Quad D Flip-Flop with

Common Clock and Reset

High–Performance Silicon–Gate CMOS

The MC54/74HC175 is identical in pinout to the LS175. The device inputs

are compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

This device consists of four D flip–flops with common Reset and Clock

inputs, and separate D inputs. Reset (active–low) is asynchronous and

occurs when a low level is applied to the Reset input. Information at a D input

is transferred to the corresponding Q output on the next positive going edge

of the Clock input.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity 166 FETs or 41.5 Equivalent Gates

LOGIC DIAGRAM

PIN 16 = VCC

PIN 8 = GND

9

4

5

12

13

CLOCK

D0

D1

D2

D3

RESET

1

DATA

INPUTS

2

3

7

6

10

11

15

14

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

INVERTING

AND

NONINVERTING

OUTPUTS

MC54/74HC175

PIN ASSIGNMENT

FUNCTION TABLE

13

14

15

16

9

10

11

12

5

4

3

2

1

8

7

6

D2

D3

Q3

Q3

VCC

CLOCK

Q2

Q2

D0

Q0

Q0

RESET

GND

Q1

Q1

D1

Inputs

Outputs

Reset

Clock

D

Q

Q

L

X

X

L

H

H

H

H

L

H

L

L

H

H

L

X

No Change

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXJ

MC74HCXXXN

MC74HCXXXD

Ceramic

Plastic

SOIC

1

16

1

16

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

1

16