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MC74HCXXXN bảng dữ liệu(PDF) 5 Page - Motorola, Inc |
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MC74HCXXXN bảng dữ liệu(HTML) 5 Page - Motorola, Inc |
5 / 13 page MC54/74HC160 MC54/74HC162 High–Speed CMOS Logic Data DL129 — Rev 6 5 MOTOROLA FUNCTION DESCRIPTION The HC160/162 are programmable 4–bit synchronous counters that feature parallel Load, synchronous or asynch- ronous Reset, a Carry Output for cascading, and count– enable controls. The HC160 and HC162 are BCD counters with asynchro- nous Reset, and synchronous Reset, respectively. INPUTS Clock (Pin 2) The internal flip–flops toggle and the output count ad- vances with the rising edge of the Clock input. In addition, control functions, such as resetting (HC162) and loading occur with the rising edge of the Clock input. Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6) These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the in- ternal flip–flops and appear at the counter outputs. P0 (pin 3) is the least–significant bit and P3 (pin 6) is the most–signifi- cant bit. OUTPUTS Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11) These are the counter outputs (BCD or binary). Q0 (pin 14) is the least–significant bit and Q3 (pin 11) is the most–signifi- cant bit. Ripple Carry Out (Pin 15) When the counter is in its maximum state (1001 for the BCD counters or 1111 for the binary counters), this output goes high, providing an external look–ahead carry pulse that may be used to enable successive cascaded counters. Rip- ple Carry Out remains high only during the maximum count state. The logic equation for this output is: Ripple Carry Out = Enable T Q0 Q1 Q2 Q3 for BCD counters HC160 and HC162 CONTROL FUNCTIONS Resetting A low level on the Reset pin (pin 1) resets the internal flip– flops and sets the outputs (Q0 through Q3) to a low level. The HC160 resets asynchronously and the HC162 resets with the rising edge of the Clock input (synchronous reset). Loading With the rising edge of the Clock, a low level on Load (pin 9) loads the data from the Preset Data Input pins (P0, P1, P2, P3) into the internal flip–flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low. Although the HC160 and HC162 are BCD counters, they may be programmed to any state. If they are loaded with a state disallowed in BCD code, they will return to their normal count sequence within two clock pulses (see the Output State Diagram). Count Enable/Disable These devices have two count–enable control pins: En- able P (pin 7) and Enable T (pin 10). The devices count when these two pins and the Load pin are high. The logic equation is: Count Enable = Enable P Enable T Load The count is either enabled or disabled by the control in- puts according to Table 1. In general, Enable P is a count– enable control; Enable T is both a count–enable and a Ripple–Carry Output control. Table 1. Count Enable/Disable Control Inputs Result at Outputs Load Enable P Enable T Q0 – Q3 Ripple Carry Out H H H Count High when Q0 – Q3 are maximum* L H H No Count High when Q0 – Q3 are maximum* X L H No Count High when Q0 – Q3 are maximum* X X L No Count L * Q0 through Q3 are maximum for the HC160 and HC162 when Q3 Q2 Q1 Q0 = 1001. HC160 and HC162 BCD Counters 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OUTPUT STATE DIAGRAMS |
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