MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1

REV 6

10/95

Triple 3-Input NOR Gate

High–Performance Silicon–Gate CMOS

The MC54/74HC27 is identical in pinout to the LS27. The device inputs

are compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 42 FETs or 10.5 Equivalent Gates

LOGIC DIAGRAM

PIN 14 = VCC

PIN 7 = GND

Y = A + B + C

A1

13

2

1

B1

C1

Y1

12

A2

5

4

3

B2

C2

Y2

6

A3

11

10

9

B3

C3

Y3

8

B

L

X

H

X

MC54/74HC27

FUNCTION TABLE

PIN ASSIGNMENT

A

L

X

X

H

11

12

13

14

8

9

10

5

4

3

2

1

7

6

B3

C3

Y1

C1

VCC

Y3

A3

B2

A2

B1

A1

GND

Y2

C2

Inputs

Output

C

L

H

X

X

Y

H

L

L

L

D SUFFIX

SOIC PACKAGE

CASE 751A–03

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

ORDERING INFORMATION

MC54HCXXJ

MC74HCXXN

MC74HCXXD

Ceramic

Plastic

SOIC

1

14

1

14

J SUFFIX

CERAMIC PACKAGE

CASE 632–08

1

14