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MC74HCXXXAD bảng dữ liệu(PDF) 4 Page - Motorola, Inc |
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MC74HCXXXAD bảng dữ liệu(HTML) 4 Page - Motorola, Inc |
4 / 12 page MC54/74HCT161A MC54/74HCT163A MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 4 FUNCTION DESCRIPTION The HCT161A/163A are programmable 4–bit synchronous counters that feature parallel Load, synchronous or asynchro- nous Reset, a Carry Output for cascading and count–enable controls. The HCT161A and HCT163A are binary counters with asynchronous Reset and synchronous Reset, respectively. INPUTS Clock (Pin 2) The internal flip–flops toggle and the output count ad- vances with the rising edge of the Clock input. In addition, con- trol functions, such as resetting and loading occur with the rising edge of the Clock input. In addition, control functions, such as resetting (HCT163A) and loading occur with the rising edge of the Clock Input. Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6) These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the internal flip–flops and appear at the counter outputs. P0 (Pin 3) is the least–significant bit and P3 (Pin 6) is the most–significant bit. OUTPUTS Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11) These are the counter outputs. Q0 (Pin 14) is the least–sig- nificant bit and Q3 (Pin 11) is the most–significant bit. Ripple Carry Out (Pin 15) When the counter is in its maximum state 1111, this output goes high, providing an external look–ahead carry pulse that may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count state. The logic equation for this output is: Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3 CONTROL FUNCTIONS Resetting A low level on the Reset pin (pin 1) resets the internal flip– flops and sets the outputs (Q0 through Q3) to a low level. The HCT161A resets asynchronously, and the HCT163A resets with the rising edge of the Clock input (synchronous reset). Loading With the rising edge of the Clock, a low level on Load (pin 9) loads the data from the Preset Data input pins (P0, P1, P2, P3) into the internal flip–flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low. Count Enable/Disable These devices have two count–enable control pins: Enable P (Pin 7) and Enable T (Pin 10). The devices count when these two pins and the Load pin are high. The logic equation is: Count Enable = Enable P • Enable T • Load The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count–enable control: Enable T is both a count–enable and a Ripple–Carry Output control. Table 1. Count Enable/Disable Control Inputs Result at Outputs Load Enable P Enable T Q0–Q3 Ripple Carry Out H H H Count High when Q0–Q3 L H H No Count are maximum* X L H No Count High when Q0–Q3 are maximum* X X L No Count L Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111. OUTPUT STATE DIAGRAM Binary Counters 0 15 14 13 12 1 2 3 4 5 6 7 8 11 10 9 |
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