công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LM4550 bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI) |
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LM4550 bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI) |
4 / 25 page Electrical Characteristics(Notes 1, 3) The following specifications apply for AV DD = 5V, DVDD = 5V, Fs = 48kHz, single codec configuration, unless otherwise noted. Limits apply for T A= 25˚C. The reference for 0dB is 1Vrms unless otherwise specified. (Continued) Symbol Parameter Conditions LM4550 Units (Limits) Typical (Note 7) Limit (Note 8) Analog to Digital Converters Resolution 18 Bits Dynamic Range (Note 2) -60dB Input THD+N, A-Weighted 90 86 dB (min) Frequency Response -1dB Bandwidth 20 kHz Digital to Analog Converters Resolution 18 Bits Dynamic Range (Note 2) -60dB Input THD+N, A-Weighted 89 85 dB (min) THD Total Harmonic Distortion V IN = -3dB, f=1kHz, RL = 10k Ω 0.01 % Frequency Response 20 - 21k Hz Group Delay (Note 2) 2 mS (max) Out of Band Energy -40 dB Stop Band Rejection 70 dB D T Discrete Tones -96 dB Output Volume and Amplifier Section A S Step Size 0dB to -46.5dB 1.5 dB A M Mute Attenuation 86 dB THD+N Headphone Amplifier Total Harmonic Distortion plus Noise Loop thru Mode R L=32, F=1KHz, P out=50mW 0.02 % Digital I/O (Note 2) V IL Low level input voltage 0.30 x DVDD V (max) V HI High level input voltage 0.40 x DVDD V (min) V OH High level output voltage 0.50 x DVDD V (min) V OL Low level output voltage 0.20 x DVDD V (max) I L Input Leakage Current AC Link inputs ±10 µA I L Tri state Leakage Current High impedance AC Link outputs ±10 µA I DR Output drive current AC Link outputs 5 mA Digital Timing Specifications (Note 2) F BC BIT_CLK frequency 12.288 MHz T BCP BIT_CLK period 81.4 nS T CH BIT_CLK high Variation of BIT_CLK period from 50% duty cycle ±20 % (max) F SYNC SYNC frequency 48 kHz T SP SYNC period 20.8 µS T SH SYNC high pulse width 1.3 µS T SL SYNC low pulse width 19.5 µS T SETUP Setup Time SDATA_IN, SDATA_OUT to falling edge of BIT_CLK 15 nS (min) T HOLD Hold Time Hold time of SDATA_IN, SDATA_OUT from falling edge of BIT_CLK 5 nS (min) T RISE Rise Time BIT_CLK, SYNC, SDATA_IN or SDATA_OUT 6 nS (max) www.national.com 4 |
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