MC54/74HC595A

High–Speed CMOS Logic Data

DL129 — Rev 6

5

MOTOROLA

FUNCTION TABLE

Oi

Inputs

Resulting Function

Operation

Reset

Serial

Input

A

Shift

Clock

Latch

Clock

Output

Enable

Shift

Register

Contents

Latch

Register

Contents

Serial

Output

SQH

Parallel

Outputs

QA – QH

Reset shift register

L

X

X

L, H,

↓

L

L

U

L

U

Shift data into shift

register

H

D

↑

L, H,

↓

L

D

→ SRA;

SRN → SRN+1

U

SRG → SRH

U

Shift register remains

unchanged

H

X

L, H,

↓

L, H,

↓

L

U

U

U

U

Transfer shift register

contents to latch register

H

X

L, H,

↓

↑

L

U

SRN → LRN

U

SRN

Latch register remains

unchanged

X

X

X

L, H,

↓

L

*

U

*

U

Enable parallel outputs

X

X

X

X

L

*

**

*

Enabled

Force outputs into high

impedance state

X

X

X

X

H

*

**

*

Z

SR = shift register contents

D = data (L, H) logic level

↑ = Low–to–High

* = depends on Reset and Shift Clock inputs

LR = latch register contents

U = remains unchanged

↓ = High–to–Low

** = depends on Latch Clock input

PIN DESCRIPTIONS

INPUTS

A (Pin 14)

Serial Data Input. The data on this pin is shifted into the

8–bit serial shift register.

CONTROL INPUTS

Shift Clock (Pin 11)

Shift Register Clock Input. A low– to–high transition on this

input causes the data at the Serial Input pin to be shifted into

the 8–bit shift register.

Reset (Pin 10)

Active–low, Asynchronous, Shift Register Reset Input. A

low on this pin resets the shift register portion of this device

only. The 8–bit latch is not affected.

Latch Clock (Pin 12)

Storage Latch Clock Input. A low–to–high transition on this

input latches the shift register data.

Output Enable (Pin 13)

Active–low Output Enable. A low on this input allows the

data from the latches to be presented at the outputs. A high

on this input forces the outputs (QA–QH) into the high–

impedance state. The serial output is not affected by this

control unit.

OUTPUTS

QA – QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)

Noninverted, 3–state, latch outputs.

SQH (Pin 9)

Noninverted, Serial Data Output. This is the output of the

eighth stage of the 8–bit shift register. This output does not

have three–state capability.