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MC74HCXXXAN bảng dữ liệu(PDF) 4 Page - Motorola, Inc |
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MC74HCXXXAN bảng dữ liệu(HTML) 4 Page - Motorola, Inc |
4 / 10 page MC54/74HC595A MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 4 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Unit Guaranteed Limit VCC V Parameter Symbol Unit v 125_C v 85_C – 55 to 25 _C VCC V Parameter Symbol tTLH, tTHL Maximum Output Transition Time, QA – QH (Figures 3 and 7) 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 31 18 15 ns tTLH, tTHL Maximum Output Transition Time, SQH (Figures 1 and 7) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns Cin Maximum Input Capacitance — 10 10 10 pF Cout Maximum Three–State Output Capacitance (Output in High–Impedance State), QA – QH — 15 15 15 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). C PDi i i C i (P P k )* Typical @ 25 °C, VCC = 5.0 V F CPD Power Dissipation Capacitance (Per Package)* 300 pF * Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input tr = tf = 6.0 ns) Sb l P V Guaranteed Limit Ui Symbol Parameter VCC V 25 _C to – 55 _C v 85_C v 125_C Unit tsu Minimum Setup Time, Serial Data Input A to Shift Clock (Figure 5) 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns tsu Minimum Setup Time, Shift Clock to Latch Clock (Figure 6) 2.0 3.0 4.5 6.0 75 60 15 13 95 70 19 16 110 80 22 19 ns th Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5) 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns trec Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 2) 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 3.0 4.5 6.0 60 45 12 10 75 60 15 13 90 70 18 15 ns tw Minimum Pulse Width, Shift Clock (Figure 1) 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns tw Minimum Pulse Width, Latch Clock (Figure 6) 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns |
Số phần tương tự - MC74HCXXXAN |
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Mô tả tương tự - MC74HCXXXAN |
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