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MC74HCXXXAD bảng dữ liệu(PDF) 5 Page - Motorola, Inc |
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MC74HCXXXAD bảng dữ liệu(HTML) 5 Page - Motorola, Inc |
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5 / 14 page  MC54/74HC160A MC54/74HC162A High–Speed CMOS Logic Data DL129 — Rev 6 5 MOTOROLA TIMING REQUIREMENTS (Input tr = tf = 6 ns) Sb l P V Guaranteed Limit Ui Symbol Parameter VCC V – 55 to 25 _C v 85_C v 125_C Unit tsu Minimum Setup Time, Preset Data Inputs to Clock (Figure 5) 2.0 3.0 4.5 6.0 150 TBD 30 26 190 TBD 38 33 225 TBD 45 38 ns tsu Minimum Setup Time, Load to Clock (Figure 5) 2.0 3.0 4.5 6.0 135 TBD 27 23 170 TBD 34 29 205 TBD 41 35 ns tsu Minimum Setup Time, Reset to Clock (HC162A only) (Figure 4) 2.0 3.0 4.5 6.0 160 TBD 32 27 200 TBD 40 34 240 TBD 48 41 ns tsu Minimum Setup Time, Enable T or Enable P to Clock (Figure 6) 2.0 3.0 4.5 6.0 200 TBD 40 34 250 TBD 50 43 300 TBD 60 51 ns th Minimum Hold Time, Clock to Preset Data Inputs (Figure 5) 2.0 3.0 4.5 6.0 50 TBD 10 9 65 TBD 13 11 75 TBD 15 13 ns th Minimum Hold Time, Clock to Load (Figure 5) 2.0 3.0 4.5 6.0 3 TBD 3 3 3 TBD 3 3 3 TBD 3 3 ns th Minimum Hold Time, Clock to Reset (HC162A only) (Figure 4) 2.0 3.0 4.5 6.0 3 TBD 3 3 3 TBD 3 3 3 TBD 3 3 ns th Minimum Hold Time, Clock to Enable T or Enable P (Figure 6) 2.0 3.0 4.5 6.0 3 TBD 3 3 3 TBD 3 3 3 TBD 3 3 ns trec Minimum Recovery Time, Reset Inactive to Clock (HC160A only) (Figure 2) 2.0 3.0 4.5 6.0 125 TBD 25 21 155 TBD 31 26 190 TBD 38 32 ns trec Minimum Recovery Time, Load Inactive to Clock (Figure 5) 2.0 3.0 4.5 6.0 125 TBD 25 21 155 TBD 31 26 190 TBD 38 32 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 3.0 4.5 6.0 80 TBD 16 14 100 TBD 20 17 120 TBD 24 20 ns tw Minimum Pulse Width, Reset (HC160A only) (Figure 2) 2.0 3.0 4.5 6.0 80 TBD 16 14 100 TBD 20 17 120 TBD 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). |
Số phần tương tự - MC74HCXXXAD |
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Mô tả tương tự - MC74HCXXXAD |
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