MC54/74HC390A

High–Speed CMOS Logic Data

DL129 — Rev 6

3

MOTOROLA

Unit

Guaranteed Limit

VCC

V

Test Conditions

Parameter

Symbol

Unit

v 125_C

v 85_C

– 55 to

25

_C

VCC

V

Test Conditions

Parameter

Symbol

VOL

Maximum Low–Level Output

Voltage

Vin = VIH or VIL

|Iout| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.40

0.40

0.40

Iin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 µA

6.0

4

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 3)

2.0

3.0

4.5

6.0

10

15

30

50

9

14

28

45

8

12

25

40

MHz

tPLH,

tPHL

Maximum Propagation Delay, Clock A to QA

(Figures 1 and 3)

2.0

3.0

4.5

6.0

70

40

20

16

80

45

25

21

90

50

30

27

ns

tPLH,

tPHL

Maximum Propagation Delay, Clock A to QC

(QA connected to Clock B)

(Figures 1 and 3)

2.0

3.0

4.5

6.0

200

160

35

30

250

185

45

40

300

210

60

50

ns

tPLH,

tPHL

Maximum Propagation Delay, Clock B to QB

(Figures 1 and 3)

2.0

3.0

4.5

6.0

70

40

20

16

80

45

25

21

90

50

30

27

ns

tPLH,

tPHL

Maximum Propagation Delay, Clock B to QC

(Figures 1 and 3)

2.0

3.0

4.5

6.0

90

56

32

25

105

70

38

31

180

100

45

40

ns

tPLH,

tPHL

Maximum Propagation Delay, Clock B to QD

(Figures 1 and 3)

2.0

3.0

4.5

6.0

70

40

20

16

80

45

25

21

90

50

30

27

ns

tPHL

Maximum Propagation Delay, Reset to any Q

(Figures 2 and 3)

2.0

3.0

4.5

6.0

80

48

28

21

95

65

32

25

110

75

40

30

ns