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Giải thích chi tiết về linh kiện  Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout
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MC74LCX573
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2
Figure 1. Pinout (Top View)
Figure 2. Logic Diagram
19
20
18
17
16
15
14
2
1
3
4567
VCC
13
8
12
9
11
10
O0
O1
O2
O3
O4
O5
O6
O7
LE
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
O0
D0
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
OE
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
11
1
PIN NAMES
Function
Output Enable Input
Latch Enable Input
Data Inputs
3−State Latch Outputs
Pins
OE
LE
D0−D7
O0−O7
TRUTH TABLE
Inputs
Outputs
OE
LE
Dn
On
Operating Mode
L
L
H
H
H
L
H
L
Transparent (Latch Disabled); Read Latch
L
L
L
L
h
l
H
L
Latched (Latch Enabled) Read Latch
L
L
X
NC
Hold; Read Latch
H
L
X
Z
Hold; Disabled Outputs
H
H
H
H
H
L
Z
Z
Transparent (Latch Disabled); Disabled Outputs
H
H
L
L
h
l
Z
Z
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level;
h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
L = Low Voltage Level
l = Low Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
NC = No Change, State Prior to the Latch Enable High−to−Low Transition
X = High or Low Voltage Level or Transitions are Acceptable
Z = High Impedance State
For ICC Reasons DO NOT FLOAT Inputs


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