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UC1825A-SP bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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UC1825A-SP bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 40 page UDG-95111 39 50- External Clock 10 6 5 R T R T C T V SYNC UDG-95110 CT 1.25 V CT from E/A Oscillator Voltage Mode Current Mode RAMP CT 7 6 1.25 V R SENSE I SWITCH from E/A Oscillator RAMP CT 7 6 11 UC1825A-SP www.ti.com SLUS873C – JANUARY 2009 – REVISED DECEMBER 2016 Product Folder Links: UC1825A-SP Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Feature Description (continued) 8.3.4 Control Methods Figure 7 shows the control methods. Figure 7. Control Methods 8.3.5 Synchronization The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor (see Figure 8). Program the free running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width must be greater than 10 ns and less than half the discharge time of the oscillator. Figure 9 shows how to synchronize two ICs, with one as master and one as slave. Figure 10 shows the waveforms in a master and slave configuration. NOTE The CLK/LEB pin no longer accepts an incoming synchronizing signal. Figure 8. General Oscillator Synchronization |
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