công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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UC1825A-SP bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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UC1825A-SP bảng dữ liệu(HTML) 4 Page - Texas Instruments |
4 / 40 page 1 INV 16 VREF 2 NI 15 VCC 3 EAOUT 14 OUTB 4 CLK/LEB 13 VC 5 RT 12 PGND 6 CT 11 OUTA 7 RAMP 10 GND 8 SS 9 ILIM Not to scale 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 INV NI EAOUT CLK/LEB RT CT RAMP SS VREF VCC OUTB VC PGND OUTA GND ILIM 4 UC1825A-SP SLUS873C – JANUARY 2009 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: UC1825A-SP Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated 6 Pin Configuration and Functions J Package 16-Pin CDIP Top View HKT Package 16-Pin CFP Top View Pin Functions PIN I/O DESCRIPTION NAME NO. CLK/LEB 4 O Output of the internal oscillator. CT 6 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor must be connected to the device ground using minimal trace length. EAOUT 3 O Output of the error amplifier for compensation. GND 10 — Analog ground return pin. ILIM 9 I Input to the current limit comparator. INV 1 I Inverting input to the error amplifier. NI 2 I Noninverting input to the error amplifier. OUTA 11 O High current totem pole output A of the on-chip drive stage. OUTB 14 O High current totem pole output B of the on-chip drive stage. PGND 12 — Ground return pin for the output driver stage. RAMP 7 I Noninverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input. RT 5 I Timing resistor connection pin for oscillator frequency programming. SS 8 I Soft-start input pin that also doubles as the maximum duty cycle clamp. VC 13 — Power supply pin for the output stage. This pin must be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths. VCC 15 — Power supply pin for the device. This pin must be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor with minimal trace lengths. VREF 16 O 5.1-V reference. For stability, the reference must be bypassed with a 0.1-μF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane. |
Số phần tương tự - UC1825A-SP_16 |
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Mô tả tương tự - UC1825A-SP_16 |
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