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ADC32RF8x bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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ADC32RF8x bảng dữ liệu(HTML) 11 Page - Texas Instruments |
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11 / 136 page  11 ADC32RF80, ADC32RF83 www.ti.com SBAS774A – MAY 2016 – REVISED DECEMBER 2016 Product Folder Links: ADC32RF80 ADC32RF83 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Overall latency = latency + tPD. (2) Latency increases when the DDC modes are used; see Table 5. (3) For latency in different DDC options, see . (4) Common-mode voltage for the SYSREF input is kept at 1.2 V. 6.10 Timing Requirements typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted) MIN NOM MAX UNIT SAMPLE TIMING Aperture delay 250 750 ps Aperture delay matching between two channels on the same device ±15 ps Aperture delay matching between two devices at the same temperature and supply voltage ±150 ps Aperture jitter, clock amplitude = 2 VPP 90 fS Latency (1) (2) Data latency, ADC sample to digital output DDC block bypassed(3), LMFS = 8224 424 Input clock cycles Fast overrange latency, ADC sample to FOVR indication on GPIO pins 70 tPD Propagation delay time: logic gates and output buffer delay (does not change with fS) 6 ns SYSREF TIMING(4) tSU_SYSREF SYSREF setup time: referenced to clock rising edge, 2949.12 MSPS 140 70 ps tH_SYSREF SYSREF hold time: referenced to clock rising edge, 2949.12 MSPS 50 20 ps Valid transition window sampling period: tSU_SYSREF – tH_SYSREF, 2949.12 MSPS 143 ps JESD OUTPUT INTERFACE TIMING UI Unit interval: 12.5 Gbps 80 100 400 ps Serial output data rate 2.5 10.0 12.5 Gbps Rise, fall times: 1-pF, single-ended load capacitance to ground 60 ps Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps 25 %UI Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps 0.99 %UI, rms Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps 9.1 %UI, pk- pk |
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