công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
STK1744-D35I bảng dữ liệu(PDF) 8 Page - List of Unclassifed Manufacturers |
|
STK1744-D35I bảng dữ liệu(HTML) 8 Page - List of Unclassifed Manufacturers |
8 / 12 page STK1744 January 2003 8 Document Control # ML0020 rev 0.0 STK1744 clock registers before reading clock data to prevent reading of data in transition. Stopping the internal register updates does not affect clock accu- racy. The updating process is stopped by writing a “1” to the read bit (the second most significant bit in the control register 7FF8), and will not restart until a “0” is written to the read bit. The RTC registers can then be read while the internal clock continues to run. Within one second after a “0” is written to the read bit, all STK1744 registers are simultaneously updated. SRAM WRITE AND SETTING THE CLOCK A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ 0-7 will be writ- ten into the memory if it is valid t DVWH before the end of a W controlled WRITE or t DVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal cir- cuitry will turn off the output buffers t WLQZ after W goes low. Setting the write bit (the MSB of the control register 7FF8) to a “1” halts updates to the STK1744 regis- ters. The correct day, date and time can then be written into the registers in 24-hour BCD format. Resetting the write bit to “0” transfers those values to the actual clock counters, after which the clock resumes normal operation. FREQUENCY TEST BIT As shown in the RTC Register Map, bit 6 of the day byte is the frequency test (FT) bit. When the FT bit is set to logic “1”, the LSB of the seconds register will toggle at 512Hz. When the seconds register is being read, the DQ 0 line will toggle at 512Hz as long as conditions for access remain valid (i.e., CE low, OE low, WE high and the address for the sec- onds register valid and stable). The FT bit must be reset to “0” in order to resume reading the time from the seconds register. CLOCK ACCURACY The STK1744 is guaranteed to be accurate to within ± 1 minute per month at 25 °C. The part requires no additional calibration, and temperature variations will have a negligible effect in most appli- cations. DATA RETENTION MODE During normal operation (V CC ≥ 4.5V), the STK1744 can be accessed with standard SRAM READ and WRITE cycles. However, when V CC falls below the power-fail voltage, V SWITCH (the voltage at which write protection occurs), access to the internal clock register and the SRAM is blocked. At this voltage, SRAM data is automatically stored to the integral Nonvolatile Elements, and power for the clock oscil- lator switches from the V CC pin to the internal capac- itor. The capacitor maintains clock activity and clock data until V CC returns to its nominal level. SOFTWARE NONVOLATILE STORE The STK1744 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initi- ated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is impor- tant that no other READ or WRITE accesses inter- vene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. Read address 0E38 (hex) Valid READ 2. Read address 31C7 (hex) Valid READ 3. Read address 03E0 (hex) Valid READ 4. Read address 3C1F (hex) Valid READ 5. Read address 303F (hex) Valid READ 6. Read address 0FC0 (hex) Initiate STORE cycle The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the SRAM will be disabled. The clock addresses may be |
Số phần tương tự - STK1744-D35I |
|
Mô tả tương tự - STK1744-D35I |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |