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MC74HCT373A bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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1 / 7 page © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 13 1 Publication Order Number: MC74HCT373A/D MC74HCT373A Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT373A may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. The HCT373A is identical in pinout to the LS373. The eight latches of the HCT373A are transparent D−type latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched. The Output Enable does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the high−impedance state. Thus, data may be latched even when the outputs are not enabled. The HCT373A is identical in function to the HCT573A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT533A, which has inverting outputs. Features • Output Drive Capability: 15 LSTTL Loads • TTL/NMOS−Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 mA • In Compliance with the Requirements Defined by JEDEC Standard No. 7 A • Chip Complexity: 196 FETs or 49 Equivalent Gates • These Devices are Pb−Free and are RoHS Compliant LOGIC DIAGRAM DATA INPUTS D0 D1 D2 D3 D4 D5 D6 D7 18 17 14 13 8 7 4 3 1 OUTPUT ENABLE 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 16 15 12 9 6 5 2 PIN 20 = VCC PIN 10 = GND NONINVERTING OUTPUTS 11 LATCH ENABLE Device Package Shipping† ORDERING INFORMATION MC74HCT373ADWG SOIC−20 (Pb−Free) 38 / Rail MC74HCT373ADWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel MC74HCT373ADTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel http://onsemi.com †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 20 MARKING DIAGRAMS SOIC−20 HCT373A AWLYYWWG HCT 373A ALYW G G TSSOP−20 20 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) SOIC−20 DW SUFFIX CASE 751D TSSOP−20 DT SUFFIX CASE 948E PIN ASSIGNMENT Q2 D1 D0 Q0 OUTPUT ENABLE GND Q3 D3 D2 Q1 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 Q6 D6 D7 Q7 VCC LATCH ENABLE Q4 D4 D5 Q5 |
Số phần tương tự - MC74HCT373A_14 |
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Mô tả tương tự - MC74HCT373A_14 |
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