11

®

ADC7802

INPUT PROTECTION

The input signal range must not exceed

±V

than 0.3V.

The analog inputs are internally clamped to V

damage to the ADC7802, the current that can flow into the

inputs must be limited to 20mA. One approach is to use an

external resistor in series with the input filter resistor. For

example, a 1k

Ω input resistor allows an overvoltage to 20V

without damage.

REFERENCE INPUTS

A 10

µF tantalum capacitor is recommended between V

and V

should be located as close as possible to the ADC7802 to

reduce dynamic errors, since the reference provides packets

of current as the successive approximation steps are carried

out.

V

fied with V

function with V

As long as there is at least a 2.5V difference between V

and V

significantly, so that accuracy will typically be within

±1LSB. (1/2LSB for a 5V span is 610µV, which is 1LSB for

a 2.5V span.)

The power supply to the reference source needs to be consid-

ered during system design to prevent V

(or overshooting) V

power-on, if the reference is not stable within 42,425 clock

cycles, an additional calibration cycle may be needed.

POWER SUPPLIES

The digital and analog power supply lines to the ADC7802

should be bypassed with 10

µF tantalum capacitors as close

to the part as possible. Although ADC7802 has excellent

power supply rejection, even for higher frequencies, linear

regulated power supplies are recommended.

Care should be taken to insure that V

before V

Figure 10 shows a good supply approach, powering both V

A

and V

between V

is also a good method to further isolate the ADC7802 from

digital supplies in a system with significant switching cur-

rents that could degrade the accuracy of conversions.

GROUNDING

To maximize accuracy of the ADC7802, the analog and

digital grounds are not connected internally. These points

should have very low impedance to avoid digital noise

feeding back into the analog ground. The V

the reference point for input signals, so it should be con-

nected directly to AGND to reduce potential noise problems.

EXTERNAL CLOCK OPERATION

The circuitry required to drive the ADC7802 clock from an

external source is shown in Figure 11a. The external clock

must provide a 0.8V max for LOW and a 3.5V min for

HIGH, with rise and fall times that do not exceed 200ns. The

minimum pulse width of the external clock must be 200ns.

Synchronizing the conversion clock to an external system

clock is recommended in microprocessor applications to

prevent beat-frequency problems.

Note that the electrical specification tables are based on

using an external 2MHz clock. Typically, the specified

accuracy is maintained for clock frequencies between 0.5

and 2.2MHz.

INTERNAL CLOCK OPERATION

Figure 11b shows how to use the internal clock generating

circuitry. The clock frequency depends only on the value of

the resistor, as shown in “Internal Clock Frequency vs

R

SFR

AIN0

AIN1

AIN2

AIN3

V

+

V

–

DGND

V

D7

D6

D5

D4

D3

V

AGND

CAL

A1

A0

CLK

BUSY

HBE

WR

CS

RD

D0

D1

D2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

REF

REF

D

A

+

10nF

10µF

+

10µF

10nF

+5V

10

Ω

5V

REF

+

10nF

10µF

FIGURE 10. Power Supply and Reference Decoupling.

FIGURE 11. Internal Clock Operation.

To ADC7802

Pin 23

CLK

74HC-Compatible

Clock Source

To ADC7802

Pin 23

+5V

R

f

11

(a) External Clock Operation

(b) Internal Clock Operation