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Silicon limitations
STM8AL3xxx STM8L052R8 STM8L1xxx6/8
10/18
DocID17922 Rev 6
1.1.6
Incorrect code execution when FLASH/EEPROM memory wakes up
from power down mode
Description
In case FLASH/EEPROM memory is put in power down mode (IDDQ), first read after
wakeup could return an incorrect content when FCPU is above 8 MHz + 5%.
FLASH/EEPROM memory is put in IDDQ mode by default during Halt mode and could be
forced to IDDQ mode by software for wait mode and during RAM execution.
As a consequence, following behavior may be seen on some devices:
After wakeup from Low power mode with FLASH memory in IDDQ mode, program
execution gets lost due to incorrect read of vector table.
Code running from RAM read an incorrect value from FLASH/EEPROM memory, when
forced in IDDQ mode.
Program execution gets corrupted when returning from RAM execution to FLASH
memory execution in case FLASH memory is forced in IDDQ mode.
Workaround
Slow down FSYSCLK before entering Low power mode to ensure correct FLASH memory
wakeup. This could be done using clock divider (CLK_CKDIVR) or by activation of fast
wakeup feature by setting FHWU bit in CLK_ICKCR register. Original clock setting can be
reconfigured back by software after wakeup.
Code example, assuming no divider is used in application by default.
CLK_CKDIVR = 0x01;
_asm(“HALT”);
CLK_CKDIVR = 0x00;
The interrupt service routine executed after wakeup could either stay at slower clock speed,
or reconfigure clock setting. Care has to be taken to restore previous clock divider at the end
of interrupt routines when modifying clock divider.
No fix planned for this limitation.


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   8-bit ultralow power MCU, up to 64 KB Flash 2 KB data EEPROM, RTC, LCD, timers, USARTs, I2C, SPIs, ADC, DAC, comparators
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