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ADAU1382 bảng dữ liệu(PDF) 11 Page - Analog Devices |
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ADAU1382 bảng dữ liệu(HTML) 11 Page - Analog Devices |
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11 / 84 page  ADAU1382 Rev. 0| Page 11 of 84 DIGITAL TIMING SPECIFICATIONS −25°C < TA < +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified. Table 7. Digital Timing Limit Parameter tMIN tMAX Unit Description MASTER CLOCK tMP 50 90.9 ns Master clock (MCLK) period (that is, period of the signal input to MCKI). Duty Cycle 30 70 % SERIAL PORT tBIL 10 ns BCLK pulse width low. tBIH 10 ns BCLK pulse width high. tLIS 5 ns LRCLK setup. Time to BCLK rising. tLIH 5 ns LRCLK hold. Time from BCLK rising. tSIS 5 ns DAC_SDATA setup. Time to BCLK rising. tSIH 5 ns DAC_SDATA hold. Time from BCLK rising. tSODM 70 ns ADC_SDATA delay. Time from BCLK falling in master mode. SPI PORT fCCLK,R 5 MHz CCLK frequency, read operation, IOVDD = 1.8 V ± 10%. fCCLK,R 10 MHz CCLK frequency, read operation, IOVDD = 3.3 V ± 10%. fCCLK,W 25 MHz CCLK frequency, write operation, IOVDD = 1.8 V ± 10%. fCCLK,W 25 MHz CCLK frequency, write operation, IOVDD = 3.3 V ± 10%. tCCPL 10 ns CCLK pulse width low. tCCPH 10 ns CCLK pulse width high. tCLS 10 ns CLATCH setup. Time to CCLK rising. tCLH 5 ns CLATCH hold. Time from CCLK rising. tCLPH 10 ns CLATCH pulse width high. tCDS 5 ns CDATA setup. Time to CCLK rising. tCDH 5 ns CDATA hold. Time from CCLK rising. tCOD 70 COUT delay from CCLK edge to valid data, IOVDD = 1.8 V ± 10%. 40 ns COUT delay from CCLK edge to valid data, IOVDD = 3.3 V ± 10%. I2C PORT fSCL 400 kHz SCL frequency. tSCLH 0.6 μs SCL high. tSCLL 1.3 μs SCL low. tSCS 0.6 μs Setup time; relevant for repeated start condition. tSCH 0.6 μs Hold time. After this period, the first clock is generated. tDS 100 ns Data setup time. tSCR 300 ns SCL rise time. tSCF 300 ns SCL fall time. tSDR 300 ns SDA rise time. tSDF 300 ns SDA fall time. tBFT 0.6 μs Bus-free time. Time between stop and start. DIGITAL MICROPHONE RL = 1 MΩ, CL = 14 pF. tDCF 10 ns Digital microphone clock fall time. tDCR 10 ns Digital microphone clock rise time. tDDV 22 30 ns Digital microphone delay time for valid data. tDDH 0 12 ns Digital microphone delay time for data three-stated. |
Số phần tương tự - ADAU1382 |
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Mô tả tương tự - ADAU1382 |
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