© Semiconductor Components Industries, LLC, 2014

July, 2014 − Rev. 8

1

Publication Order Number:

MC14518B/D

MC14518B, MC14520B

Dual Up Counters

The MC14518B dual BCD counter and the MC14520B dual binary

counter are constructed with MOS P−channel and N−channel

enhancement mode devices in a single monolithic structure. Each

consists of two identical, independent, internally synchronous 4−stage

counters. The counter stages are type D flip−flops, with interchangeable

Clock and Enable lines for incrementing on either the positive−going or

negative−going transition as required when cascading multiple stages.

Each counter can be cleared by applying a high level on the Reset line.

In addition, the MC14518B will count out of all undefined states within

two clock periods. These complementary MOS up counters find

primary use in multi−stage synchronous or ripple counting applications

requiring low power dissipation and/or high noise immunity.

Features

Clock or Negative Transition on Enable

Schottky TTL Load Over the Rated Temperature Range

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

Symbol

Parameter

Value

Unit

DC Supply Voltage Range

− 0.5 to +18.0

V

Input or Output Voltage Range

(DC or Transient)

V

Input or Output Current

(DC or Transient) per Pin

±10

mA

Power Dissipation,

per Package (Note 2)

500

mW

Operating Temperature Range

− 55 to +125

°C

Storage Temperature Range

− 65 to +150

°C

Lead Temperature

(8−Second Soldering)

260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating: “D/DW” Package: –7.0 mW/

_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be

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xx

= 18 or 20

A

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W

= Work Week

G

= Pb−Free Indicator

MARKING DIAGRAM

SOIC−16 WB

DW SUFFIX

CASE 751G

1

16

145xxB

AWLYYWWG

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

PIN ASSIGNMENT

13

14

15

16

9

10

11

12

5

4

3

2

1

8

7

6