MC14536B

http://onsemi.com

8

Figure 7. Power Dissipation Test

Circuit and Waveform

Figure 8. Switching Time Test Circuit and Waveforms

0.01

mF

CERAMIC

500

mF

PULSE

GENERATOR

SET

RESET

8-BYPASS

C INH

MONO-IN

OSC INH

C

B

A

D

OUT 1

OUT

2

DECODE

OUT

20 ns

20 ns

90%

10%

50%

50%

DUTY CYCLE

PULSE

GENERATOR

SET

RESET

8-BYPASS

C INH

MONO-IN

OSC INH

C

B

A

D

OUT 1

OUT

2

DECODE

OUT

20 ns

20 ns

50%

50%

90%

10%

OUT

FUNCTIONAL TEST SEQUENCE

Test function (Figure 9) has been included for the

reduction of test time required to exercise all 24 counter

stages. This test function divides the counter into three

8−stage sections and 255 counts are loaded in each of the

8−stage sections in parallel. All flip−flops are now at a “1”.

The counter is now returned to the normal 24−stages in

which will cause the counter to ripple from an all “1” state

to an all “0” state.

Figure 9. Functional

Test Circuit

PULSE

GENERATOR

SET

RESET

8-BYPASS

C INH

MONO-IN

OSC INH

C

B

A

D

OUT 1

OUT

2

DECODE

OUT

FUNCTIONAL TEST SEQUENCE

Inputs

Outputs

Comments

Set

Reset

8−Bypass

Decade Out

Q1 thru Q24

All 24 stages are in Reset mode.

1

0

1

1

0

1

1

1

1

0

Counter is in three 8 stage sections in parallel mode.

0

1

1

1

0

First “1” to “0” transition of clock.

1

0

−

−

−

1

1

1

255 “1” to “0” transitions are clocked in the counter.

0

1

1

1

1

The 255 “1” to “0” transition.

0

0

0

0

1

Counter converted back to 24 stages in series mode.

Set and Reset must be connected together and simultaneously

go from “1” to “0”.

1

0

0

0

1

0

0

0

0

0

Counter Ripples from an all “1” state to an all “0” state.