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II.2 Power up

⁄ down control:

It is recommended that all programmable functions (excluding the gain controls) are set while the device is

powered down. Power state control can then be included in the last programming instruction (the power up bit

PU is located in the last address register (CR18) so that the multi-byte mode of the control interface can be

easily used to program all the required functions before power up).

When a power up command is given, all the circuits needed for the selected mode are activated (in Voice mode

the DX output will remain in the high impedance state until the second FS pulse after power up arrives). A built-in

power consumption management function keeps in power down the blocks that are not needed by the selected

operating mode.

II.3 Power down state:

Following a period of activity, power down state may be reentered by writing 0 in bit PU in CR18. All the Control

In addition to the power down instruction, the detection of absence of the current Master Clock (no transition

detected) automatically puts the device in power down state without setting bit PU. If transitions on the master

clock are detected the device is put again in power up.

II.4 Voice Transmit section:

This section is active in Voice Mode. Voice Transmit analog preamplifier gain is designed in two stages to

enable gains up to 42.5 dB. Stage 1 provides a selectable 0 or 20 dB gain via bit PG in CR4. Stage 2 is a

programmable gain amplifier which provides from 0 to 22.5 dB of additional gain in 1.5dB step. It can be

programmed with bits TXA in CR4. Two differential microphone inputs (MIC1P

⁄ N, MIC2P ⁄ N) and one single

ended line input (MIC3) are provided. The line input MIC3 can only be used with preamplifier gain set to 0dB in

both stages. The microphone input or Transmit Mute is selected with bits MS in CR4. In the Mute case, the

analog transmit signal is grounded. A separate MBIAS output can be used to bias a microphone (bit MB in CR4).

An active anti-alias filter then precedes the single bit

Σ∆ analog to digital converter that is followed by an 8th

order IIR digital TX channel filter. The TX channel filter is band-pass if the FS frequency is 8kHz and low-pass

if the FS frequency is 16kHz (bit VFS in CR0). A precision on chip voltage reference ensures accurate and highly

stable transmission levels. Any offset voltage arising in the analog blocks is cancelled by an internal autozero

circuit. Voice data is sent to the PCM I

⁄ F to be serially sent to DX output.

II.5 Voice Receive section:

This section is active in Voice Mode. Voice Data coming from PCM I

⁄ F DR pin is sent to the 8th order digital

IIR RX channel filter. The filter can be selected to be band-pass or low-pass, with bit HPB in CR5, when FS

frequency is 8kHz, while it is always low-pass when FS frequency is 16kHz. The filter is followed by a

Σ∆ digital

to analog converter and a 3rd order switched-capacitor reconstruction filter. The Sidetone can be summed to

the received signal (bit SI in CR5) and its amplitude can be programmed with bits SA in CR5.

II.6 Stereo Audio DAC section:

interpolated with an FIR filter in order to feed the oversampled multi-bit

Σ∆ modulator, the digital to analog

converter is followed by a 3rd order switched-capacitor reconstruction filter.

II.7 Output Drivers section:

There are 3 Analog Output Drivers. The LSP

⁄ N differential driver delivers 190mW typical power with 0.1%

T.H.D. (140mW minimum undistorted) on a 8

Ω earpiece ⁄ loudspeaker (piezoceramic loads up to 50nF can also

be driven, with a series resistor), it has a 30dB range gain control (bits LSA in CR7). The 2 single ended drivers

(HPL and HPR) deliver 20mW typical power with 0.1% T.H.D. (16.5mW minimum undistorted) on 30

Ω stereo

headphones, they have a 40dB range gain control (CR8 for HPL and CR9 for HPR). It is possible to put all the

drivers in power-down, enable the LSP

⁄ N one, enable the HPL one or enable HPL and HPR together