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MC14551B bảng dữ liệu(PDF) 1 Page - ON Semiconductor

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Giải thích chi tiết về linh kiện  Quad 2-Channel Analog Multiplexer/Demultiplexer
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© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 9
1
Publication Order Number:
MC14551B/D
MC14551B
Quad 2-Channel Analog
Multiplexer/Demultiplexer
The MC14551B is a digitally−controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved.
Features
Triple Diode Protection on All Control Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Analog Voltage Range (VDD − VEE) = 3.0 to 18 V
Note: VEE must be
≤ VSS
Linearized Transfer Characteristics
Low Noise − 12 nV√Cycle, f ≥ 1.0 kHz typical
For Low RON, Use The HC4051, HC4052, or HC4053 High−Speed
CMOS Devices
Switch Function is Break Before Make
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
(Referenced to VEE, VSS ≥ VEE)
VDD
– 0.5 to + 18.0
V
Input or Output Voltage (DC or Transient)
(Referenced to VSS for Control Input and
VEE for Switch I/O)
Vin, Vout
– 0.5 to VDD
+ 0.5
V
Input Current (DC or Transient),
per Control Pin
Iin
±10
mA
Switch Through Current
Isw
±25
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
– 55 to + 125
_C
Storage Temperature Range
Tstg
– 65 to + 150
_C
Lead Temperature (8–Second Soldering)
TL
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: −7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD for control inputs and VEE ≤ (Vin or Vout)
≤ VDD for Switch I/O.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS, VEE or VDD). Unused outputs must be left open.
MARKING DIAGRAM
SOIC−16
D SUFFIX
CASE 751B
1
16
14551BG
AWLYWW
http://onsemi.com
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
Z1
Z
W
W0
VDD
CONTROL
Y1
Z0
X
X1
X0
W1
VSS
VEE
Y0
Y
PIN ASSIGNMENT


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