6V49205B_16 datasheet(5/16 Pages) IDT

tên linh kiện	6V49205B

Giải thích chi tiết về linh kiện	Freescale System Clock w/Selectable DDR Frequency

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nhà sản xuất	IDT [Integrated Device Technology]

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REVISION R 11/23/16

5

FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY

6V49205B DATASHEET

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 6V49205B. These ratings, which are standard

values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other

conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the

recommended operating temperature range.

Electrical Characteristics - Input/Supply/Common Output DC Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Maximum Supply Voltage

VDDxxx

Supply Voltage

4.6

V

1

Maximum Input Voltage

VIH

Referenced to GND

VDD + 0.5

V

1

Minimum Input Voltage

VIL

Referenced to GND

GND - 0.5

V

1

Storage Temperature

Ts

-

-65

150

°C

JunctionTemperature

Tj

-

125

°C

1

Input ESD protection

ESD prot

Human Body Model

2000

V

1

1 Operation under these conditions is neither implied, nor guaranteed.

NOTES on Absolute Max Parameters

TAMB = -40 to +85°C; VDD = 3.3 V +/-5%, All outputs driving test loads (unless noted otherwise).

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Ambient Operating Temp

TAMB

--40

25

85

°C

Supply Voltage

VDDxxx

Supply Voltage

3.135

3.3

3.465

V

Power supply Ramp Time

TPWRRMP

Power supply ramp must be montonic

4

ms

Latched Input High Voltage

VIH_LI

Single-ended Latched Inputs

2.1

VDD + 0.3

V

Latched Input Low Voltage

VIL_LI

Single-ended Latched Inputs

VSS - 0.3

0.8

V

Input Leakage Current

IIN

VIN = VDD , VIN = GND

-5

5

uA

2

Operating Supply Current

IDDOP3.3

All outputs loaded and running

119

155

mA

Input Frequency

Fi

23

25

27

MHz

3

Pin Inductance

Lpin

57

nH

CIN

Logic Inputs

1.5

3

5

pF

COUT

Output pin capacitance

5

6

pF

CINX

X1 & X2 pins

5

6

pF

Clk Stabilization

TSTAB

From VDD Power-Up or de-assertion of PD

to 1st clock

3.2

5

ms

Tfall_SE

TFALL

10

ns

1

Trise_SE

TRISE

10

ns

1

SMBus Voltage

VDD

2.7

3.3

V

Low-level Output Voltage

VOLSMB

@ IPULLUP

0.4

V

Current sinking at

VOLSMB = 0.4 V

IPULLUP

SMB Data Pin

4

mA

SCLK/SDATA

Clock/Data Rise Time

TRI2C

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

ns

SCLK/SDATA

Clock/Data Fall Time

TFI2C

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

ns

SMBus Operating Frequency

FSMBUS

400

kHz

1 Signal is required to be monotonic in this region.

2 Input leakage current does not include inputs with pull-up or pull-down resistors

Input Capacitance

Fall/rise time of all 3.3V control inputs from

20-80%

NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

3 For margining purposes only. Normal operation should have Fin =25MHz

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