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ADS8325IBDGKR bảng dữ liệu(PDF) 6 Page - Burr-Brown (TI) |
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ADS8325IBDGKR bảng dữ liệu(HTML) 6 Page - Burr-Brown (TI) |
6 / 21 page ADS8325 6 SBAS226A www.ti.com D OUT 1.4V Test Point 3k Ω 100pF C LOAD Load Circuit for t dDO, tr, and tf Voltage Waveforms for D OUT Rise and Fall Times, tr, tf Voltage Waveforms for D OUT Delay Times, tdDO Voltage Waveforms for t dis Voltage Waveforms for t en Load Circuit for t dis and ten t r D OUT 90% 10% t f D OUT Test Point t dis Waveform 2, ten V CC t dis Waveform 1 100pF C LOAD 3k Ω t dis CS/SHDN DOUT Waveform 1(1) DOUT Waveform 2(2) 90% 10% 90% 4 1 B15 5 t en CS/SHDN DCLOCK D OUT t dDO D OUT DCLOCK t hDO NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. Timing Diagrams and Test Circuits for the Parameters in the Timing Characteristics table. CS/SHDN D OUT DCLOCK Complete Cycle Power Down Conversion Sample Use positive clock edge for data transfer t SUCS t CONV t SMPL NOTE: A minimum of 22 clock cycles are required for 16-bit conversion. Shown are 24 clock cycles. If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again. B15 (MSB) B14 B13 B12 B11 B10 B9 B8 B0 (LSB) B7 B1 B6 B2 B5 B3 B4 Hi-Z 0 Hi-Z t CSD TIMING CHARACTERISTICS SYMBOL DESCRIPTION MIN TYP MAX UNITS tSMPL Analog Input Sample Time 4.5 5.0 Clk Cycles tCONV Conversion Time 16 Clk Cycles tCYC Throughput Rate 100 kHz tCSD CS Falling to DCLOCK LOW 0ns tSUCS CS Falling to DCLOCK Rising 20 ns tHDO DCLOCK Falling to Current DOUT Not Valid 5 15 ns tDIS CS Rising to DOUT Tri-State 70 100 ns tEN DCLOCK Falling to DOUT Enabled 20 50 ns tF DOUT Fall Time 5 25 ns tR DOUT Rise Time 7 25 ns TIMING DIAGRAMS |
Số phần tương tự - ADS8325IBDGKR |
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Mô tả tương tự - ADS8325IBDGKR |
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