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LM5170QPHPRQ1 bảng dữ liệu(PDF) 10 Page - Texas Instruments |
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LM5170QPHPRQ1 bảng dữ liệu(HTML) 10 Page - Texas Instruments |
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10 / 67 page  10 LM5170-Q1 SNVSAQ6 – NOVEMBER 2016 www.ti.com Product Folder Links: LM5170-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Electrical Characteristics (continued) FOSC = 100 kHz; VVCC = 10 V; VVIN = VHV-Port = 48 V and VLV-Port = 12 V, unless otherwise stated. (1) PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT INTERLEAVE PHASE DELAY FROM CH-2 To CH-1 (OPT) VOPTL OPT input low state 1 V VOPTH OPT input high state 2 V HO2 on-time rising edge versus HO1 on-time rising edge, or LO2 on-time rising edge versus LO1 on-time rising edge VOPT > 2 V for 2, 4, 6, and 8 phases 175 180 185 Degrees VOPT < 1 V for 3 phases 235 240 245 Internal pulldown impedance 1 MΩ DEAD TIME (DT) tDT LO falling edge to HO rising edge delay RDT = 7.5 kΩ 40 ns tDT HO falling edge to LO rising edge delay RDT = 7.5 kΩ 40 ns VDT DC voltage level for programming 1.25 V VDT DC voltage for adaptive dead time scheme only (short DT to VCCA) VCCA V VADPT HO-SW or LO-GND voltage threshold to enable cross output for adaptive dead time scheme VVCC > 9 V, (VHB – VSW) > 8 V, HO or LO voltage falling 1.5 V tADPT LO falling edge to HO rising edge delay VDT = VVCC 36 ns tADPT HO falling edge to LO rising edge delay VDT = VVCC 41 ns SOFT START (SS) ISS SS charging current source VSS = 0 V 25 µA VSS-OFFS SS to PWM comparator offset SS – PWM comparator noninverting input 1 V RSS SS discharge device RDS(on) VSS = 2 V 30 Ω VSS_LOW SS discharge completion threshold Once it is discharged by internal logic 0.23 V DIODE EMULATION Current zero cross threshold Current sense voltage 0 mV CKT BREAKER CONTROL (BRKG, BRKS) IBRKG Sourcing current nFAULT = 5 v, VVIN = 24 V, VBRKS = 12 V 275 330 375 µA VBRK-CLP Voltage clamp nFAULT= 5 V, VVIN = 48 V, VBRKS = 12 V 9 14 V RBRK-SINK Sinking capability nFAULT = 0 V 20 Ω VREADY BRKG to BRKS voltage threshold to indicate readiness for operation Rising edge 6.5 8.5 V IBRKG-LEAK BRKG leakage current nFAULT= 5 V, VVIN – VBRKS = 0 V, VBRKG – VBRKS = 10 V 10 µA FAULT ALARM (nFAULT) In normal operation, no fault 4 5 V Internal pull-up impedance for normal operation 30 k Ω Internal pull-down FET RDS(on) after fault detected 125 Ω External pull-down voltage threshold for IC shutdown 1 V tFAULT External pul-ldown glitch filter 2 µs td1_FAULT Delay time of nFAULT pull-down below 1 V to (VBRKG – VBRKS) < 1.5 V 5 µs td2_FAULT Start-up fault detection duration VUVLO > 2.6 V, VVCC > 9 V 3 ms THERMAL SHUTDOWN TSD Thermal shutdown 175 ºC TSD-HYS Thermal shutdown hysteresis 25 ºC |
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