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LM5170QPHPRQ1 bảng dữ liệu(PDF) 5 Page - Texas Instruments |
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LM5170QPHPRQ1 bảng dữ liệu(HTML) 5 Page - Texas Instruments |
5 / 67 page 5 LM5170-Q1 www.ti.com SNVSAQ6 – NOVEMBER 2016 Product Folder Links: LM5170-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O(1) DESCRIPTION NO. NAME 33 BRKS O Connect to the common source of the circuit breaker MOSFET pair. When the circuit breaker function is disabled, simply connect to AGND through a 20-kΩ resistor. 34 BRKG O Connect to the gate pins of the circuit breaker MOSFET pair. Once the LM5170-Q1 is enabled, an internal 330- µA current source starts to charge the circuit breaker MOSFET gates. The BRKG to BRKS voltage is internally clamped at 12 V. 35 CSB1 I CH-1 differential current sense inputs. The CSA1 pin connects to the CH-1 power inductor. The CSB1 pin connects to the circuit breaker, or directly to the LV-Port if the circuit breaker is not used. The CH-1 current sense resistor is placed between these two current sense pins. An internal 1-M Ω resistor is connected between the CSB1 and OVPB pins through an internal cutoff switch. During operation, the cutoff switch is closed and this internal resistor pulls up the OVPB pins. In shutdown mode, the internal resistor is disconnected by the cutoff switch. 36 CSA1 I 37 IOUT1 O CH-1 inductor current monitor pin. A current source proportional to the CH-1 inductor current flows out of this pin. Placing a terminating resistor and filter capacitor from IOUT1 to AGND produces a DC voltage representing the CH-1 DC current level. An internal 25-µA offset DC current source at the IOUT1 pin raises the active signal to be above the ground noise, thus improving the monitor noise immunity. 38 IOUT2 O CH-2 inductor current monitor pin. A current proportional to the CH-2 inductor current flows out of this pin. Placing a terminating resistor and filter capacitor from IOUT2 to AGND produces a DC voltage representing the CH-2 DC current level. An internal 25-µA offset DC current source at the IOUT2 pin raises the active signal above the ground noise, thus improving the monitor noise immunity. 39 EN1 I CH-1 enable pin. Pulling EN1 above 2.4 V turns off the SS pulldown and allows CH-1 to begin a soft-start sequence. Pulling EN1 below 1 V discharges the SS capacitor and holds it low. The high- and low-side gate drivers of both channels are held in the low state when SS is discharged. 40 SYNCIN I Input for an external clock that overrides the free-running internal oscillator. The SYNCIN pin can be left open or grounded when it is not used. 41 SYNCOUT O Clock output pin and fault check mode selector. SYNCOUT is connected to the downstream LM5170-Q1 in a 3- or 4-phase configuration. It also functions as a circuit breaker selection pin during start-up. Placing a 10-k Ω resistor from the SYNCOUT to AGND pins disables the fault check. feature. If no resistor is connected from SYNCOUT to AGND, the fault check is enabled. 42 ISETD I The PWM current programming pin. The inductor DC current level is proportional to the PWM duty cycle. Use either ISETA or ISETD but not both for channel current programming. When ISETD is not used, short ISETD to AGND. 43 EN2 I CH-2 enable pin. Pulling EN2 above 2.4 V enables CH-2. Pulling EN2 below 1 V shuts down the HO2 and LO2 drivers. 44 DIR I Direction command input. Pulling DIR above 2 V sets the converter to the buck mode, which commands the current to flow from the HV-Port to LV-Port. Pulling DIR below 1 V sets the converter to the boost mode, which commands the current to flow from the LV-Port to HV-Port. If the DIR pin is left open, the LM5170-Q1 detects an invalid command and disables both channels with the MOSFET gate drivers in the low state. 45 ISETA I, O The analog current programming pin. The inductor DC current is proportional to the ISETA voltage. Use either ISETA or ISETD but not both for channel current programming. When ISETA is not used, connect a 100-pF to 0.1-µF capacitor from ISETA to AGND. 46 AGND G Analog ground reference. AGND must connect to PGND externally through a single point connection to improve the LM5170-Q1 noise immunity. 47 OSC I The internal oscillator frequency is programmed by a resistor between OSC and AGND. 48 DT I A resistor connected between DT and AGND sets the dead time between the high-side and low-side driver outputs. Tie the DT pin to VCCA to activate the internal adaptive dead time control. — EP — Exposed pad of the package. No internal electrical connections. Must be soldered to the large ground plane to reduce thermal resistance. |
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