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LM5170-Q1 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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LM5170-Q1 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 67 page  4 LM5170-Q1 SNVSAQ6 – NOVEMBER 2016 www.ti.com Product Folder Links: LM5170-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O(1) DESCRIPTION NO. NAME 8 RAMP2 I The inverting input of the CH-2 PWM Comparator. An external RC circuit tied between VINX, RAMP2, and AGND forms the ramp generator producing a ramp signal proportional to the HV-Port voltage, thus achieving a voltage feedforward function. The RAMP2 capacitor voltage is reset to AGND at the end of every switching cycle. 9 OVPA I Connected to the noninverting input of the HV-Port overvoltage comparator. An internal 3-MΩ pullup resistor and an external resistor across the OVPA and AGND pins form a divider that senses the HV-Port voltage. When the OVPA pin voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the overvoltage condition is removed. 10 ULVO I The UVLO pin serves as the master enable pin. When UVLO is pulled below 1.25 V, the entire LM5170-Q1 is in a low quiescent current shutdown mode. When UVLO is pulled above 1.25 V but below 2.5 V, the LM5170-Q1 enters the initialization stage in which the nFAULT pin is first pulled up to 5 V, while the rest of the LM5170-Q1 is kept in the OFF state. When UVLO is pulled above the 2.5 V, the LM5170-Q1 enters a MOSFET failure detection stage. If no failure is detected, the circuit breaker gate driver (BRKS and BRKG) turns on, and the LM5170-Q1 enables the oscillator and RAMP generator, and stands by until the EN1 and EN2 commands enable the channel. 11 COMP2 O Output of the CH-2 trans-conductance (gm) error amplifier and the noninverting input of the CH-2 PWM comparator. A loop compensation network must be connected to this pin. 12 SS I The soft-start programming pin. An external capacitor and an internal 25-μA current source set the ramp rate of the COMP pins voltage during soft start. If CH-2 is enabled after CH-1 completes soft start, the CH-2 turnon will not be controlled by the SS pin. 13 SW2 I CH-2 switch node. Connect to the CH-2 high-side MOSFET source, the low-side MOSFET drain, and the bootstrap capacitor return terminal. 14 HB2 P CH-2 high-side gate driver bootstrap supply input. 15 HO2 I/O CH-2 high-side gate driver output. 16 NC — No Connect 17 LO2 I/O CH-2 low-side gate driver output. 18 PGND G Power ground connection pin for the low-side gate drivers and external VCC bias supply. 19 VCC I/P VCC bias supply pin, powering the drivers. An external bias supply between 9 V to 12 V must be applied across the VCC and PGND pins. 20 LO1 I/O CH-1 low-side gate driver output. 21 NC — No Connect 22 HO1 I/O CH-1 high-side gate driver output. 23 HB1 P CH-1 high-side gate driver bootstrap supply input. 24 SW1 I CH-1 switch node. Connect to the CH-1 high-side MOSFET source, the low-side MOSFET drain, and the bootstrap capacitor return terminal. 25 OVPB I Connected to the noninverting input of the LV-Port overvoltage comparator. An internal 1-M Ω pullup resistor and an external resistor across the OVPB and AGND pins form the divider that senses the LV-Port voltage. When the converter operates in Boost mode the OVPB pin status is ignored. In Buck mode, when the OVPB pin voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the overvoltage condition is removed. 26 COMP1 O Output of the CH-1 trans-conductance (gm) error amplifier and the noninverting input of the CH-1 PWM comparator. A loop compensation network must be connected to this pin. 27 nFAULT I/O Fault flag pin or external shutdown pin. When a MOSFET drain-to-source short circuit failure is detected before start-up, the nFAULT pin will be internally pulled low to report the short-circuit failure, and the LM5170-Q1 will remain in a disabled state. The nFAULT pin can also be externally pulled low to shut down the LM5170-Q1, serving as a forced shutdown pin. In forced shutdown, all gate drivers turn off, and nFAULT is latched low until the UVLO pin is pulled below 1.25 V to release the latch and initiate a new start-up. 28 RAMP1 I The inverting input of the CH-1 PWM comparator. An external RC circuit tied between VINX, RAMP1, and AGND forms the ramp generator producing a ramp signal proportional to the HV-Port voltage, thus achieving a voltage feedforward function. The RAMP1 capacitor voltage is reset to AGND at the end of every switching cycle. 29 OPT I Multiphase configuration pin. Tied to either VCCA or AGND, the OPT pin sets the phase lag of the SYNCOUT signal corresponding to 4 phase or 3 phase operation, respectively. 30 IPK I A resistor connected between IPK and AGND sets the threshold for the cycle-by-cycle current limit comparator 31 VCCA I/P Analog bias supply pin. Connect VCCA to VCC through an external 25- Ω resistor. A low-pass filter capacitor is required from the VCCA pin to AGND. 32 NC — No Connect. |
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