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FDC37N869 bảng dữ liệu(PDF) 9 Page - SMSC Corporation |
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FDC37N869 bảng dữ liệu(HTML) 9 Page - SMSC Corporation |
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9 / 147 page  SMSC DS – FDC37N869 Page 9 Rev. 11/09/2000 PIN DESCRIPTION BUFFER TYPE PER PIN Table 1 - DESCRIPTION OF PIN FUNCTIONS TQFP PIN # NAME SYMBOL BUFFER MODE 6 DESCRIPTION HOST PROCESSOR INTERFACE 46-49 51-54 Data Bus 0- 7 D0-D7 IO12 The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode. 42 nI/O Read nIOR IS This active low signal is issued by the host microprocessor to indicate an I/O read operation. 43 nI/O Write nIOW IS This active low signal is issued by the host microprocessor to indicate an I/O write operation. 44 Address Enable AEN IS Active high Address Enable indicates DMA operations on the host data bus. Used internally to qualify appropriate address decodes. 26-32 39-41, 95,35, 36,1, 3,25 Address Bus A0-A15 I These host address bits determine the I/O address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. All internal address decodes use the full A0 to A15 address bits. 19,50, 97,17 DMA Request A, B, C, D DRQ_A DRQ_B DRQ_C DRQ_D O12 These active high outputs are the DMA request for byte transfers of data between the host and the chip. These signals are cleared on the last byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). 20,34, 94,22 nDMA Acknowl- edge A, B, C, D nDACK_A nDACK_B nDACK_C nDACK_D IS These are active low inputs acknowledging the request for a DMA transfer of data between the host and the chip. These inputs enable the DMA read or write internally. 33 Terminal Count TC IS This signal indicates that DMA data transfer is complete. TC is only accepted when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low. 37 Serial IRQ SIRQ IO12 Serial IRQ pin used with the CLK33 pin to transfer FDC37N869 interrupts to the host. 38 PCI Clock CLK33 ICLK 33MHz PCI clock input, used with the SIRQ and the nCLKRUN pins to serially transfer FDC37N869 interrupts to the host. 55 Reset RESET_ DRV IS This active high signal resets the chip and must be valid for 500ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. 98 I/O Channel Ready (Note 4) IOCHRDY OD12 This pin is pulled low to extend the read/write command. IOCHRDY can used by the IRCC and by the Parallel Port in EPP mode. FLOPPY DISK INTERFACE 14 nRead Disk Data nRDATA IS Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. |
Số phần tương tự - FDC37N869 |
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Mô tả tương tự - FDC37N869 |
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