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BU2152FS bảng dữ liệu(PDF) 7 Page - Rohm |
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7 / 16 page 7/12 BU2152FS TSZ02201-0RHR1GZ00150-1-2 © 2014 ROHM Co., Ltd. All rights reserved. 24.Aug.2015 Rev.002 www.rohm.com TSZ22111・15・001 Timing Chart 1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 24 data bits into the DATA terminal. 2. P1 to P24 parallel output data of the shift register is set after the 24 th clock by the LCK. 3. Since the STB is a level trigger latch, data is retained in the “H” section and renewed in the “L” section of the STB. 4. The final stage data of the shift register is outputted to the SO by synchronizing with the rise time of the CLK. [ Truth Table] Input Function CLK STB CLB × × L All the data of the latch circuit are set to “H” (data of shift register does not change), all the parallel outputs are “H”. H H Serial data of DATA pin are latched to the shift register. At this time, the data of the latch circuit does not change. L L H The data of the shift register are transferred to the latch circuit, and the data of the latch circuit are outputted from the parallel output pin. H The data of the shift register shifts 1bit, and the data of the latch circuit and parallel output also change. CLK DATA DATA24 DATA23 DATA22 DATA2 DATA1 P1~P24 Previous DATA DATA SO Previous DATA24 Previous DATA23 Previous DATA2 DATA24 Previous DATA1 DATA23 DATA22 STB Figure 5. Timing Chart |
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